Yamazaki H., Akeno I., Nobori K., Asai T., and Ando K., "Proposal and evaluation of recurrent neural network training by multi-phase qua ntization optimizer," Nonlinear Theory and Its Applications, vol. E16-N, no. 1, (2025), in press.
Akeno I., Yamazaki H., Asai T., and Ando K., "Multi-phase-quantization optimizer and its architecture for edge AI training," Nonlinear Theory and Its Applications, vol. E16-N, no. 1, (2025), in press.
Arai F., Hori A., Marukame T., Asai T., and Ando K., "Common Bases Hypothesis: exploring multi-task collaborative learning of neural networks," Nonlinear Theory and Its Applications, vol. , (2025), in press.
Nobori K., Yamazaki H., Marukame T., Asai T., and Ando K., "Evaluation of the encoder-decoder model's common representation acquisition t oward its application in edge computing," Nonlinear Theory and Its Applications, vol. , (2025), in press.
Minagawa K., Ando K., and Asai T., "Performance evaluation of Bayesian neural networks in detecting out-of-distribution image data and a study on data preprocessing," Nonlinear Theory and Its Applications, vol. E15-N, no. 4, pp. 709-724 (2024).
Kojima S., Minagawa K., Saito T., Ando K., and Asai T., "Acquisition of physical kinetics of permanent magnet DC motor by reservoir computing," Nonlinear Theory and Its Applications, vol. E15-N, no. 4, pp. 899-909 (2024).
Saito T., Ando K., and Asai T., "Extending binary neural networks to Bayesian neural networks with probabilistic interpretation of binary weights," IEICE Transactions on Information and Systems, vol. E107-D, no. 8, pp. 949-957 (2024).
Muramatsu S., Nishida K., Ando K., and Asai T., " Stochastic memory device based on a bistable system model with a simple analog circuit," Nonlinear Theory and Its Applications, vol. E15-N, no. 2, pp. 249-261 (2024).
Hagiwara N., Kunimi T., Ando K., Akai-Kasaya M., and Asai T., "Design and evaluation of brain-inspired predictive coding networks based on the free-energy principle for novel neuromorphic hardware," Nonlinear Theory and Its Applications, vol. E15-N, no. 1, pp. 107-118 (2024).
Yamakawa S., Ando K., Akai-Kasaya M., and Asai T., "A novel small-signal detection method using divergence properties of second-order linear differential equations," Electronics Letters, vol. 59, no. 16, e12928 (2023).
Hagiwara N., Asai T., Ando K., and Akai-Kasaya M., "Fabrication and training of 3D conductive polymer networks for neuromorphic wetware," Advanced Functional Materials, vol. 33, no. 42, 02300903 (2023).
Yan J., Ando K., Yu J., and Motomura M., "TT-MLP: Tensor Train Decomposition on Deep MLPs," IEEE Access, vol. 11, pp. 10398-10411 (2023).
Jimbo S., Okonogi D., Ando K., Chu T.V., Yu J., Motomura M., and Kawamura K., "A Hybrid Integer Encoding Method for Obtaining High-quality Solutions of Quadratic Knapsack Problems on Solid-state Annealers," IEICE Transactions on Information and Systems, vol. E105-D, no. 12, pp. 2019-2031 (2022).
Suzuki J., Kaneko T., Ando K., Hirose K., Kawamura K., Chu T.V., Motomura M., and Yu J., "ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation," International Journal of Networking and Computing, vol. 11, no. 2, pp. 338-353 (2021).
Yamamoto K., Kawamura K., Ando K., Mertig N., Takemoto T., Yamaoka M., Teramoto H., Sakai A., Takamaeda-Yamazaki S., and Motomura M., "STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin–Spin Interactions," IEEE Journal of Solid-State Circuits, vol. 56, no. 1, pp. 165-178 (2020).
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Dither NN: hardware/algorithm co-design for accurate quantized neural networks," IEICE Transactions on Information and Systems, vol. E102, pp. 2341-2353 (2019).
Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Hamada M., Kuroda T., and Motomura M., "QUEST: Multi-purpose log-quantized DNN inference engine stacked on 96-MB 3-D SRAM using inductive coupling technology in 40-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 186-196 (2019).
Hirose K., Uematsu R., Ando K., Ueyoshi K., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "Quantization error-based regularization for hardware-aware neural network training," Nonlinear Theory and Its Applications, vol. E9-N, no. 4, pp. 453-465 (2018).
Ando K., Ueyoshi K., Orimo K., Yonekawa H., Sato S., Nakahara H., Takamaeda-Yamazaki S., Ikebe M., Asai T., Kuroda T., and Motomura M., "BRein memory: a single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4TOPS at 0.6W," IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 983-994 (2018).
Ando K., Takamaeda-Yamazaki S., Ikebe M., Asai T., and Motomura M., "A multithreaded CGRA for convolutional neural network processing," Circuits and Systems, vol. 8, no. 6, pp. 149-170 (2017).
安藤 洸太, "Edge-side deep neural network processors: quantization, communication, and memories ," 電子情報通信学会複雑コミュニケーションサイエンス研究会, Hokkaido University, Sapporo, Japan (Aug. 4-5, 2022).
安藤 洸太, " ニューラルネットワークプロセッサ技術とモデル構築・学習方法およびFPGAへの実装法 ~デモ付~," 日本テクノセンター オンラインセミナー, Nihon Techno Center(オンライン), Tokyo, Japan (Jul. 20, 2022).
安藤 洸太, "⼆値・三値・量⼦化ニューラルネットワークの推論LSIと学習アルゴリズム," 第44回 多値論理フォーラム, Online, Japan (Sep. 11-12, 2021).
国際会議
Matsuno S., Abe Y., Ando K., and Asai T., "Physical reservoir computing on discrete analog CMOS circuits and its application to real data analysis and prediction," IEEE ICRC 2024, Carté Hotel , San Diego, USA (Dec. 16-17, 2024).
Kunimi T., Ando K., Marukame T., and Asai T., "Predictive coding networks consisting of analog electronic circuits based on the free-energy principle," The 27th SNU-HU Joint Symposium, Seoul National University, Seoul, Korea (Nov. 28, 2024).
Hori A., Arai F., Inoue Y., Marukame T., Asai T., and Ando K., "Variable-parallelism reconfigurable architecture for neural networks," The 27th SNU-HU Joint Symposium, Seoul National University, Seoul, Korea (Nov. 28, 2024).
Matsuno S., Abe Y., Ando K., and Asai T., "Numerical performance evaluation of analog electronic reservoir circuits with discrete CMOS devices," The 27th SNU-HU Joint Symposium, Seoul National University, Seoul, Korea (Nov. 28, 2024).
Tatsumi S., Ando K., and Asai T., "Replication of Physical Reservoir Computers," The 27th SNU-HU Joint Symposium, Seoul National University, Seoul, Korea (Nov. 28, 2024).
Minagawa K., Saito T., Kojima S., Ando K., and Asai T., "Out-of-distribution data detection using Bayesian convolutional neural network with variational inference," International Joint Conference on Neural Networks (IJCNN 2024), PACIFICO Yokohama, Yokohama, Japan (Jun. 30-Jul. 5, 2024).
Akeno I., Yamazaki H., Asai T., and Ando K., "Edge AI online training architecture using multi-phase-quantization optimizer," International Joint Conference on Neural Networks (IJCNN 2024), PACIFICO Yokohama, Yokohama, Japan (Jun. 30-Jul. 5, 2024).
Minagawa K., Saito T., Kojima S., Ando K., and Asai T., "Out-of-distribution detection using Bayesian neural network toward hardware implementation," The 5th International Symposium on Neuromorphic AI Hardware, RIHGA Royal Hotel Kokura, Kitakyushu, Japan (Mar. 1-2, 2024).
Kunimi T., Hagiwara N., Ando K., and Asai T., "A novel dynamic predictive coding network with augmented direct feedback alignment towards its physical implementation," The 5th International Symposium on Neuromorphic AI Hardware, RIHGA Royal Hotel Kokura, Kitakyushu, Japan (Mar. 1-2, 2024).
Akeno I., Yamazaki H., Asai T., and Ando K., "Edge AI online training architecture using multi-phase-quantization optimizer," The 5th International Symposium on Neuromorphic AI Hardware, RIHGA Royal Hotel Kokura, Kitakyushu, Japan (Mar. 1-2, 2024).
Hsiao W.-J., Asai T., Lu D., and Ando K., "A Novel Near-memory computing architecture for recurrent neural networks with SRAM and RRAM," The 5th International Symposium on Neuromorphic AI Hardware, RIHGA Royal Hotel Kokura, Kitakyushu, Japan (Mar. 1-2, 2024).
Kojima S., Minagawa K., Saito T., Ando K., and Asai T., "Acquisition of physical kinetics of machines by reservoir computing and its applications to anomaly detection," The 12th RIEC International Symposium on Brain Functions and Brain Computer, Research Institute of Electrical Communication, Tohoku University, Sendai, Japan (Feb. 27-28, 2024).
Yamakawa S., Ando K., and Asai T., "Evaluation of a nonlinear small signal detection circuit for a neuromorphic membrane using alginate gel," In-material Computing Workshop for Young Researchers, p. 16, PA-11, Hokkaido Jichiro Kaikan, Sapporo, Japan (Nov. 14, 2023).
Yamakawa S., Ando K., Akai-Kasaya M., and Asai T., "A novel nonlinear small-signal detection circuit using divergence properties of second-order linear differential equations," Proceedings of the 5th International Conference on Microelectronics Devices & Technology (MicDAT' 2023), pp. 17-19, Pestana Casino Park Hotel, Funchal, Portugal (Sep. 20-22, 2023).
Hagiwara N., Asai T., Ando K., and Akai-Kasaya M., "Growth of 3D conductive polymer fiber networks towards neuromorphic wetware," Neuromorphic Organic Devices, Hotel Elbresidenz, Bad Schandau, Germany (Sep. 18-20, 2023).
Suzuki J., Yu J., Yasunaga M., Lopez Garcia-Arias A., Okoshi Y., Kumazawa S., Ando K., Kawamura K., Chu T.V., and Motomura M., "Pianissimo: A sub-mW class DNN accelerator with progressive bit-by-bit datapath architecture for adaptive inference at edge," 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Rihga Royal Hotel Kyoto, Kyoto, Japan (Jun. 11-16, 2023).
Kawamura K., Yu J., Okonogi D., Jimbo S., Inoue G., Hyodo A., Lopez Garcia-Arias A., Ando K., Fukushima-Kimura B.H., Yasudo R., Chu T.V., and Motomura M., "Amorphica: 4-replica 512 fully connected spin 336MHz metamorphic annealer with programmable optimization strategy and compressed-spin-transfer multi-chip extension," 2023 International Solid-State Circuits Conference (ISSCC 2023), San Francisco Marriott Marquis, San Francisco, US (Feb. 19-23, 2023).
Yamakawa S., Ando K., Akai-Kasaya M., and Asai T., "Design and evaluation of brain-computer communication devices using divergence properties of non-linear dynamical systems," The 9th Japan-Korea Joint Workshop on Complex Communication Sciences, Lahan Select, Gyeong Ju, Korea (Jan. 4-6, 2023).
Hagiwara N., Asai T., Ando K., and Akai-Kasaya M., "3D conductive polymer wiring synapses for neuromorphic wetware," The 4th International Symposium on Neuromorphic AI Hardware, ART HOTEL Kokura New Tagawa, Kitakyushu, Japan (Dec. 13-14, 2022).
Okoshi Y., Lopez Garcia-Arias A., Hirose K., Ando K., Kawamura K., Chu T.V., Motomura M., and Yu J., "Multicoated Supermasks Enhance Hidden Networks," 39th International Conference on Machine Learning, Baltimore Convention Center, Baltimore, USA (Jul. 17-23, 2022).
Hirose K., Yu J., Ando K., Okoshi Y., Lopez Garcia-Arias A., Suzuki J., Chu T.V., Kawamura K., and Motomura M., "Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet," 2022 International Solid-State Circuits Conference (ISSCC 2022), Online, San Francisco, USA (Mar. 20-24, 2022).
Ando K., Yu J., Hirose M., Nakahara H., Kawamura K., Chu T.V., and Motomura M., "Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner," 2021 IEEE Hot Chips 33 Symposium, Online, Palo Alto, USA (Aug. 22-24, 2021).
Shiba K., Omori T., Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Motomura M., Hamada M., and Kuroda T., "A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Online, Seville, Spain (Oct. 10-21, 2020).
Suzuki J., Ando K., Hirose K., Kawamura K., Chu T.V., Motomura M., and Yu J., "ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation," 2020 Eighth International Symposium on Computing and Networking (CANDAR), Online, Naha, Japan (Sep. 24-27, 2020).
Yamamoto K., Ando K., Mertig N., Takemoto T., Yamaoka M., Teramoto H., Sakai A., Takamaeda-Yamazaki S., and Motomura M., "STATICA: A 512-spin 0.25M-weight full-digital annealing processor with a near-memory all-spin-updates-at-once architecture for combinatorial optimization with complete spin-spin interactions," 2020 International Solid-State Circuits Conference (ISSCC 2020), San Francisco Marriott Marquis, San Francisco, USA (Feb. 16-20, 2020).
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Dither NN: an accurate neural network with dithering for low bit-precision hardware," The 2018 International Conference on Field-Programmable Technology (FPT'18), Tenbusu-Naha Hall, Naha, Japan (Dec. 10-14, 2018).
Kudo T., Ueyoshi K., Ando K., Hirose K., Uematsu R., Oba Y., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "Area and energy optimization for bit-serial log-quantized DNN Accelerator with shared accumulators," IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, Vietnam National University, Hanoi, Vietnam (Sep. 12-14, 2018).
Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Kadomoto J., Miyata T., Hamada M., Kuroda T., and Motomura M., "QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS," 2018 International Solid-State Circuits Conference (ISSCC 2018), San Francisco Marriott Marquis, San Francisco, US (Feb. 11-15, 2018).
Hirose K., Uematsu R., Ando K., Orimo K., Ueyoshi K., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Logarithmic Compression for Memory Footprint Reduction in Neural Network Training," 5th International Workshop on Computer Systems and Architectures (CSA 2017), Aomori Prefecture Tourist Center, Aomori, Japan (Nov. 19-22, 2017).
Ando K., Ueyoshi K., Hirose K., Orimo K., Yonekawa H., Sato S., Nakahara H., Ikebe M., Takamaeda-Yamazaki S., Asai T., Kuroda T., and Motomura M., "In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks," 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017), Tufts University, Boston, USA (Aug. 6-9, 2017).
Ando K., Ueyoshi K., Orimo K., Yonekawa H., Sato S., Nakahara H., Ikebe M., Asai T., Takamaeda-Yamazaki S., Kuroda T., and Motomura M., "BRein memory: a 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS," 2017 Symposia on VLSI Technology and Circuits, Rihga Royal Hotel, Kyoto, Japan (Jun. 5-8, 2017).
Ueyoshi K., Ando K., Orimo K., Ikebe M., Asai T., and Motomura M., "Exploring optimized accelerator design for binarized convolutional neural networks," The 2017 International Joint Conference on Neural Networks, William A. Egan Civic and Convention Center, Alaska, USA (May 14-19, 2017).
Ando K., Ueyoshi K., Orimo K., Ikebe M., Takamaeda-Yamazaki S., Asai T., and Motomura M., "Throughput analysis of a data-flow reconfigurable array architecture for convolutional neural networks," The 5th RIEC International Symposium on Brain Functions and Brain Computer, Tohoku University, Sendai, Japan (Feb. 27-28, 2017).
Orimo K., Ando K., Ueyoshi K., Ikebe M., Asai T., and Motomura M., "FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting," 2016 International Conference on Reconfigurable Computing and FPGAs, Iberostar Cancun hotel, Cancun, Mexico (Nov. 30-Dec. 2, 2016).
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda S., and Motomura M., "Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware," FPT'18 - Best Paper Award, Dec. 13, 2018.
Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Kadomoto J., Miyata T., Hamada M., Kuroda T., and Motomura M., "QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS," ISSCC 2018 Silkroad Award, Feb. 11, 2018.