卒業生とその進路

Neuromorphic CMOS circuits implementing a novel neural segmentation model based on symmetric STDP learning


福田 駿

2006 年度 卒 /学士(工学)

卒業研究の概要

Humans can distinguish multiple sensory sources that coincide. Recent discoveries of synchronous oscillations in the visual and auditory cortex have triggered much interest in exploring oscillatory correlation to solve the problems of neural segmentation. Many neural models that perform segmentation have been proposed, but they are often difficult to be implemented on practical integrated circuits. Therefore in my study, I designed a simple neural segmentation model that is suitable for analog complementary metal-oxide-semiconductor (CMOS) circuits.

My segmentation model consists of mutually-coupled neural oscillators exhibiting synchronous (or asynchronous) oscillations. All the neurons are coupled with each other through positive or negative synaptic connections. Each neuron accepts external inputs, e.g., sound inputs in the frequency domain, and oscillates (or does not oscillate) when the input amplitude is higher (or lower) than a given threshold value. Our basic idea is to strengthen (or weaken) the synaptic weights between synchronous (or asynchronous) neurons, which may result in phase-domain segmentation. The synaptic weights are updated based on symmetric spike-timing dependent plasticity (STDP) using a correlation neural network that is suitable for analog CMOS implementation. I numerically demonstrated basic operations the proposed model, as well as fundamental circuit operations using a simulation program with integrated circuit emphasis (SPICE).

学術論文

  1. Fukuda E.S., Inoue H., Takenaka T., Kim D., Sadahisa T., Asai T., and Motomura M., "Enhancing memcached by caching its data and functionalities at network interface," IPSJ Journal, vol. 56, no. 3, pp. 143-152 (2015).
  2. Kim D., Hida I., Fukuda E.S., Asai T., and Motomura M., "Reducing power and energy consumption of nonvolatile microcontrollers with transparent on-chip instruction cache," Circuits and Systems, vol. 5, no. 11, pp. 253-264 (2014).
  3. Fukuda E.S., Kawashima H., Inoue H., Asai T., and Motomura M., "C-based design of window join for dynamically reconfigurable hardware," Journal of Computer Science and Engineering, vol. 20, no. 2, pp. 1-9 (2013).
  4. Fukuda E.S., Tovar G.M., Asai T., Hirose T., and Amemiya Y., "Neuromorphic CMOS circuits implementing a novel neural segmentation model based on symmetric STDP learning," Journal of Signal Processing, vol. 11, no. 6, pp. 439-444 (2007).

書籍/チャプター

  1. Tovar G.M., Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "Analog CMOS circuits implementing neural segmentation model based on symmetric STDP learning," Neural Information Processing, Ishikawa M., Doya K., Miyamoto H., and Yamakawa T., Eds., Lecture Notes in Computer Science, vol. 4985, pp. 117-126, Springer, Berlin / Heidelberg (2008).

招待講演/セミナー

  1. 福田 駿 エリック, 本村 真人, "ソフトウェア記述によるハードウェアストリーム処理," 2013年度筑波大学DB meets FPGAセミナー, University of Tsukuba, Tsukuba, Japan (Apr. 26, 2013).
  2. 福田 駿 エリック, 本村 真人, "C言語によるSTPエンジンへの適応型ストリーム処理システムの実装," 2013年度ルネサスエレクトロニクス リコンフィギュラブル技術セミナー, Renesas Electronics Corp., Kawasaki, Japan (Apr. 19, 2013).

国際会議

  1. Yamamoto K., Fukuda E.S., Asai T., and Motomura M., "An accelerator for frequent Itemset mining from data stream with parallel item tree," The 19th Workshop on Synthesis And System Integration of Mixed Information Technologies, Evergreen Resort Hotel, Yilan, Taiwan (Mar. 16-17, 2015).
  2. Fukuda E.S., Inoue H., Takenaka T., Kim D., Sadahisa T., Asai T., and Motomura M., "Achieving higher performance of memcached by caching at network interface," The 2014 International Conference on Field Programmable Technology, Parkyard Hotel, Shanghai, China (Dec. 10-12, 2014).
  3. Kim D., Hida I., Fukuda E.S., Asai T., and Motomura M., "A study of transparent on-chip instruction cache for NV microcontrollers," The 7th International Conference on Advances in Circuits, Electronics and Micro-electronics, Mercure Lisboa, Lisbon, Portugal (Nov. 16-20, 2014).
  4. Kim D., Fukuda E.S., Sadahisa T., Asai T., and Motomura M., "Hardware architecture for accelerating key-value retrieval implemented on FPGA," The 3rd Japan-Korea Joint Workshop on Complex Communication Sciences, Paradise Hotel, Busan, Korea (Oct. 27-28, 2014).
  5. Fukuda E.S., Inoue H., Takenaka T., Kim D., Sadahisa T., Asai T., and Motomura M., "Caching memcached at reconfigurable network interface," The 24th International Conference on Field Programmable Logic and Applications, Technische Universität München, Munich, Germany (Sep. 2-4, 2014).
  6. Fukuda E.S., Takenaka T., Inoue H., Kawashima H., Asai T., and Motomura M., "High level synthesis with stream query to C parser: Eliminating hardware development difficulties for software developers," Proceedings of the 18th Workshop on Synthesis And System Integration of Mixed Information Technologies, pp. 310-315, Hotel Sapporo Garden Palace, Sapporo, Japan (Oct. 21-22, 2013).
  7. Fukuda E.S., Kawashima H., Inoue H., Asai T., and Motomura M., "Exploiting hardware reconfigurability on window join," The 2013 International Conference on High Performance Computing & Simulation, Hilton Strand Hotel, Helsinki, Finland (Jul. 1-5, 2013).
  8. Fukuda E.S., Kawashima H., Inoue H., Fujii T., Furuta K., Asai T., and Motomura M., "C-based adaptive stream processing on dynamically reconfigurable hardware: window join case study," The 9th International Symposium on Applied Reconfigurable Computing, Courtyard Marriott Los Angeles, Los Angeles, U.S.A. (Mar. 25-27, 2013).
  9. Tovar G.M., Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "Analog CMOS circuits implementing neural segmentation model based on symmetric STDP learning," Proceedings of the 14th International Conference on Neural Information Processing, pp. 306-315, Kitakyushu, Japan (Nov. 13-16, 2007).
  10. Tovar G.M., Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "Neuromorphic CMOS circuits implementing a novel neural segmentation model based on symmetric STDP learning," Proceedings of the 2007 International Joint Conference on Neural Networks, pp. 897-901, Florida, U.S.A. (Aug. 12-17, 2007).
  11. Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "A novel segmentation model for neuromorphic CMOS circuits," Proceedings of the 2007 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 489-492, Shanghai, China (Mar. 3-6, 2007).

受賞

  1. Kim D., Fukuda E.S., Sadahisa T., Asai T., and Motomura M., "Hardware architecture for accelerating key-value retrieval implemented on FPGA," The 3rd Japan-Korea Joint Workshop on Complex Communication Sciences - Best Student Paper Award, Oct. 28, 2014.
  2. 福田 駿 エリック, "二重キャッシングによるMemcached高速化の提案," 2013年度電子情報通信学会コンピュータシステム研究会 - 優秀若手講演賞, 2014年6月9日.
  3. Fukuda E.S., "A novel segmentation model for neuromorphic CMOS circuits," The Research Institute of Signal Processing - NSCP'07 Student Paper Award, Mar. 2007.

国内学会

  1. 山本 佳生, 定久 紀基, 金 多厚, 福田 駿 エリック, 浅井 哲也, 本村 真人, "頻出アイテムセットマイニング高速化のためのストリームプロセッサ," LSIとシステムのワークショップ, 北九州国際会議場, (北九州市), 2015年5月11-13日.
  2. 定久 紀基, 山本 佳生, 金 多厚, 福田 駿 エリック, 浅井 哲也, 本村 真人, "Locality-Sensitive HashingのスケーラブルなハードウェアアーキテクチャのFPGA実装," 電子情報通信学会総合大会, 立命館大学びわこ・くさつキャンパス, (草津), 2015年3月10-13日.
  3. 定久 紀基, 山本 佳生, 金 多厚, 福田 駿 エリック, 浅井 哲也, 本村 真人, "類似検索を行うLocality-Sensitive Hashingのスケーラブルなハードウェアアーキテクチャ," 電子情報通信学会集積回路研究会・コンピュータシステム研究会合同 平成26年度若手研究会, 機械振興会館, (東京), 2014年12月1-2日.
  4. 定久 紀基, 福田 駿 エリック, 浅井 哲也, 本村 真人, "実データ統計を用いた動的なMemcached評価用ロードジェネレータ," 電子情報通信学会総合大会, 新潟大学 五十嵐キャンパス, (新潟), 2014年3月18-21日.
  5. 福田 駿 エリック, 定久 紀基, 井上 浩明, 竹中 崇, 浅井 哲也, 本村 真人, "二重キャッシングによるMemcached高速化の提案," 電子情報通信学会 リコンフィギャラブルシステム研究会, 慶応義塾大学, (日吉), 2014年1月28-29日.
  6. 福田 駿 エリック, 川島 英之, 井上 浩明, 藤井 太郎, 古田 浩一朗, 浅井 哲也, 本村 真人, "リコンフィギュラブルハードウェアを用いた高速ストリーム処理の一検討," 電子情報通信学会 リコンフィギャラブルシステム研究会, 北陸先端科学技術大学院大学, (能美), 2013年9月18-19日.
  7. 福田 駿 エリック, 川島 英之, 井上 浩明, 浅井 哲也, 本村 真人, "C言語による動的リコンフィギュラブルハードウェアへのWindow Joinの実装," 電子情報通信学会 情報ネットワーク研究会, (福井), 2013年6月.
  8. 福田 駿 エリック, "自律的協調ロボットの集団形状化ルール:単純構造から超複雑構造の自己組織化へ向けて," データ駆動型生命情報科学の挑戦-スーパーコンピュータ「京」と生命情報科学の接点-, (仙台), 2012年5月.