Neuromorphic CMOS circuits implementing a novel neural segmentation model based on symmetric STDP learning
福田 駿
2006 年度 卒 ／学士（工学）
卒業研究の概要
Humans can distinguish multiple sensory sources that coincide. Recent discoveries of synchronous oscillations in the visual and auditory cortex have triggered much interest in exploring oscillatory correlation to solve the problems of neural segmentation. Many neural models that perform segmentation have been proposed, but they are often difficult to be implemented on practical integrated circuits. Therefore in my study, I designed a simple neural segmentation model that is suitable for analog complementary metal-oxide-semiconductor (CMOS) circuits.
My segmentation model consists of mutually-coupled neural oscillators exhibiting synchronous (or asynchronous) oscillations. All the neurons are coupled with each other through positive or negative synaptic connections. Each neuron accepts external inputs, e.g., sound inputs in the frequency domain, and oscillates (or does not oscillate) when the input amplitude is higher (or lower) than a given threshold value. Our basic idea is to strengthen (or weaken) the synaptic weights between synchronous (or asynchronous) neurons, which may result in phase-domain segmentation. The synaptic weights are updated based on symmetric spike-timing dependent plasticity (STDP) using a correlation neural network that is suitable for analog CMOS implementation. I numerically demonstrated basic operations the proposed model, as well as fundamental circuit operations using a simulation program with integrated circuit emphasis (SPICE).
学術論文
Fukuda E.S., Inoue H., Takenaka T., Kim D., Sadahisa T., Asai T., and Motomura M., "Enhancing memcached by caching its data and functionalities at network interface," IPSJ Journal, vol. 56, no. 3, pp. 143-152 (2015).
Kim D., Hida I., Fukuda E.S., Asai T., and Motomura M., "Reducing power and energy consumption of nonvolatile microcontrollers with transparent on-chip instruction cache," Circuits and Systems, vol. 5, no. 11, pp. 253-264 (2014).
Fukuda E.S., Kawashima H., Inoue H., Asai T., and Motomura M., "C-based design of window join for dynamically reconfigurable hardware," Journal of Computer Science and Engineering, vol. 20, no. 2, pp. 1-9 (2013).
Fukuda E.S., Tovar G.M., Asai T., Hirose T., and Amemiya Y., "Neuromorphic CMOS circuits implementing a novel neural segmentation model based on symmetric STDP learning," Journal of Signal Processing, vol. 11, no. 6, pp. 439-444 (2007).
書籍／チャプター
Tovar G.M., Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "Analog CMOS circuits implementing neural segmentation model based on symmetric STDP learning," Neural Information Processing, Ishikawa M., Doya K., Miyamoto H., and Yamakawa T., Eds., Lecture Notes in Computer Science, vol. 4985, pp. 117-126, Springer, Berlin / Heidelberg (2008).
招待講演／セミナー
福田 駿 エリック, 本村 真人, "ソフトウェア記述によるハードウェアストリーム処理," 2013年度筑波大学DB meets FPGAセミナー, University of Tsukuba, Tsukuba, Japan (Apr. 26, 2013).
Fukuda E.S., Inoue H., Takenaka T., Kim D., Sadahisa T., Asai T., and Motomura M., "Achieving higher performance of memcached by caching at network interface," The 2014 International Conference on Field Programmable Technology, Parkyard Hotel, Shanghai, China (Dec. 10-12, 2014).
Kim D., Fukuda E.S., Sadahisa T., Asai T., and Motomura M., "Hardware architecture for accelerating key-value retrieval implemented on FPGA," The 3rd Japan-Korea Joint Workshop on Complex Communication Sciences, Paradise Hotel, Busan, Korea (Oct. 27-28, 2014).
Fukuda E.S., Takenaka T., Inoue H., Kawashima H., Asai T., and Motomura M., "High level synthesis with stream query to C parser: Eliminating hardware development difficulties for software developers," Proceedings of the 18th Workshop on Synthesis And System Integration of Mixed Information Technologies, pp. 310-315, Hotel Sapporo Garden Palace, Sapporo, Japan (Oct. 21-22, 2013).
Fukuda E.S., Kawashima H., Inoue H., Fujii T., Furuta K., Asai T., and Motomura M., "C-based adaptive stream processing on dynamically reconfigurable hardware: window join case study," The 9th International Symposium on Applied Reconfigurable Computing, Courtyard Marriott Los Angeles, Los Angeles, U.S.A. (Mar. 25-27, 2013).
Tovar G.M., Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "Analog CMOS circuits implementing neural segmentation model based on symmetric STDP learning," Proceedings of the 14th International Conference on Neural Information Processing, pp. 306-315, Kitakyushu, Japan (Nov. 13-16, 2007).
Tovar G.M., Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "Neuromorphic CMOS circuits implementing a novel neural segmentation model based on symmetric STDP learning," Proceedings of the 2007 International Joint Conference on Neural Networks, pp. 897-901, Florida, U.S.A. (Aug. 12-17, 2007).
