北海道大学 大学院情報科学研究院

卒業生とその進路

A Study on Acceleration Methods of Data Center Applications with Reconfigurable Hardware


福田 駿

2014 年度 卒 ／博士（工学）
平成26年度 日本学術振興会特別研究員

博士論文の概要

This study discusses the use of reconfigurable hardware, especially in data centers.

Reconfigurable hardware is a promising technology for overcoming the difficulties face by general-purpose processors, which have been central to computer science for decades. Enabling reconfigurable technology to be used by a variety of people, including software developers, will have a great impact on pushing current computing to a new era. The recent enthusiasm for cloud computing indicates the increasing significance of data centers, and improving the performance of data centers in computation speed and energy efficiency has a great impact on the entire computer industry.

Although computers have progressed enormously since their invention, physical restriction is beginning to prevent them from achieving higher computation speed and energy efficiency. These two matrices, computation speed and energy efficiency, are critical in data centers that handle gigantic data traffic from all over the world. As the amount of data that data centers handle is growing even more, computer developers need different ways of improving computers. Among the several alternatives that have been proposed, reconfigurable hardware is one of the most suitable choices, and this is what we try to use in this study. Reconfigurable hardware promises higher performance and energy efficiency in many application domains, and several research groups have been trying to deploy it in data centers.

Meanwhile, reconfigurable hardware is used mainly by embedded or networking device vendors, and curious end users often simply enjoy trying them with reconfigurable boards purchased on their own. This is because it is difficult to obtain higher performance with inexpensive reconfigurable boards, which an individual can buy, than with a commercially available general-purpose processor, and reconfigurable boards that can exceed the performance of commercial general-purpose processor are too expensive for end users to buy individually. By deploying reconfigurable hardware and making it available to the public, the cost of utilizing reconfigurable hardware will go down and thus more end-users will be eager to use it. More applications such as databases that require very low latency will be built on reconfigurable hardware as well as general-purpose processors. Such a computing system, which uses several general-purpose processors and reconfigurable devices or heterogeneous systems, is too complicated for end users' everyday use.

As a consequence, to make the system look simple for the end users, it will become more transparent: they will eventually not notice which kind of computing device they are using. However, there are many problems that must be solved before such a cloud system can be widely used. Among them, we focus on two major problems in this study: developing applications with reconfigurable hardware is more difficult compared to software applications, thus, the cost of developing the application is higher; and a method for using reconfigurable hardware in data centers is not established.

In order to solve the first problem, we assess where the difficulties lie in the state of the art design method that uses high-level synthesis tools for developing hardware accelerated application systems, and propose a method to overcome the difficulties. For solving the other problem, we propose a new technique of using reconfigurable hardware in data centers.

学術論文

  1. Fukuda E.S., Inoue H., Takenaka T., Kim D., Sadahisa T., Asai T., and Motomura M., "Enhancing memcached by caching its data and functionalities at network interface," IPSJ Journal, vol. 56, no. 3, pp. 143-152 (2015).
  2. Kim D., Hida I., Fukuda E.S., Asai T., and Motomura M., "Reducing power and energy consumption of nonvolatile microcontrollers with transparent on-chip instruction cache," Circuits and Systems, vol. 5, no. 11, pp. 253-264 (2014).
  3. Fukuda E.S., Kawashima H., Inoue H., Asai T., and Motomura M., "C-based design of window join for dynamically reconfigurable hardware," Journal of Computer Science and Engineering, vol. 20, no. 2, pp. 1-9 (2013).
  4. Fukuda E.S., Tovar G.M., Asai T., Hirose T., and Amemiya Y., "Neuromorphic CMOS circuits implementing a novel neural segmentation model based on symmetric STDP learning," Journal of Signal Processing, vol. 11, no. 6, pp. 439-444 (2007).

書籍／チャプター

  1. Tovar G.M., Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "Analog CMOS circuits implementing neural segmentation model based on symmetric STDP learning," Neural Information Processing, Ishikawa M., Doya K., Miyamoto H., and Yamakawa T., Eds., Lecture Notes in Computer Science, vol. 4985, pp. 117-126, Springer, Berlin / Heidelberg (2008).

招待講演／セミナー

  1. 福田 駿 エリック, 本村 真人, "ソフトウェア記述によるハードウェアストリーム処理," 2013年度筑波大学DB meets FPGAセミナー, University of Tsukuba, Tsukuba, Japan (Apr. 26, 2013).
  2. 福田 駿 エリック, 本村 真人, "C言語によるSTPエンジンへの適応型ストリーム処理システムの実装," 2013年度ルネサスエレクトロニクス リコンフィギュラブル技術セミナー, Renesas Electronics Corp., Kawasaki, Japan (Apr. 19, 2013).

国際会議

  1. Yamamoto K., Fukuda E.S., Asai T., and Motomura M., "An accelerator for frequent Itemset mining from data stream with parallel item tree," The 19th Workshop on Synthesis And System Integration of Mixed Information Technologies, Evergreen Resort Hotel, Yilan, Taiwan (Mar. 16-17, 2015).
  2. Fukuda E.S., Inoue H., Takenaka T., Kim D., Sadahisa T., Asai T., and Motomura M., "Achieving higher performance of memcached by caching at network interface," The 2014 International Conference on Field Programmable Technology, Parkyard Hotel, Shanghai, China (Dec. 10-12, 2014).
  3. Kim D., Hida I., Fukuda E.S., Asai T., and Motomura M., "A study of transparent on-chip instruction cache for NV microcontrollers," The 7th International Conference on Advances in Circuits, Electronics and Micro-electronics, Mercure Lisboa, Lisbon, Portugal (Nov. 16-20, 2014).
  4. Kim D., Fukuda E.S., Sadahisa T., Asai T., and Motomura M., "Hardware architecture for accelerating key-value retrieval implemented on FPGA," The 3rd Japan-Korea Joint Workshop on Complex Communication Sciences, Paradise Hotel, Busan, Korea (Oct. 27-28, 2014).
  5. Fukuda E.S., Inoue H., Takenaka T., Kim D., Sadahisa T., Asai T., and Motomura M., "Caching memcached at reconfigurable network interface," The 24th International Conference on Field Programmable Logic and Applications, Technische Universität München, Munich, Germany (Sep. 2-4, 2014).
  6. Fukuda E.S., Takenaka T., Inoue H., Kawashima H., Asai T., and Motomura M., "High level synthesis with stream query to C parser: Eliminating hardware development difficulties for software developers," Proceedings of the 18th Workshop on Synthesis And System Integration of Mixed Information Technologies, pp. 310-315, Hotel Sapporo Garden Palace, Sapporo, Japan (Oct. 21-22, 2013).
  7. Fukuda E.S., Kawashima H., Inoue H., Asai T., and Motomura M., "Exploiting hardware reconfigurability on window join," The 2013 International Conference on High Performance Computing & Simulation, Hilton Strand Hotel, Helsinki, Finland (Jul. 1-5, 2013).
  8. Fukuda E.S., Kawashima H., Inoue H., Fujii T., Furuta K., Asai T., and Motomura M., "C-based adaptive stream processing on dynamically reconfigurable hardware: window join case study," The 9th International Symposium on Applied Reconfigurable Computing, Courtyard Marriott Los Angeles, Los Angeles, U.S.A. (Mar. 25-27, 2013).
  9. Tovar G.M., Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "Analog CMOS circuits implementing neural segmentation model based on symmetric STDP learning," Proceedings of the 14th International Conference on Neural Information Processing, pp. 306-315, Kitakyushu, Japan (Nov. 13-16, 2007).
  10. Tovar G.M., Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "Neuromorphic CMOS circuits implementing a novel neural segmentation model based on symmetric STDP learning," Proceedings of the 2007 International Joint Conference on Neural Networks, pp. 897-901, Florida, U.S.A. (Aug. 12-17, 2007).
  11. Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "A novel segmentation model for neuromorphic CMOS circuits," Proceedings of the 2007 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 489-492, Shanghai, China (Mar. 3-6, 2007).

受賞

  1. Kim D., Fukuda E.S., Sadahisa T., Asai T., and Motomura M., "Hardware architecture for accelerating key-value retrieval implemented on FPGA," The 3rd Japan-Korea Joint Workshop on Complex Communication Sciences - Best Student Paper Award, Oct. 28, 2014.
  2. 福田 駿 エリック, "二重キャッシングによるMemcached高速化の提案," 2013年度電子情報通信学会コンピュータシステム研究会 - 優秀若手講演賞, 2014年6月9日.
  3. Fukuda E.S., "A novel segmentation model for neuromorphic CMOS circuits," The Research Institute of Signal Processing - NSCP'07 Student Paper Award, Mar. 2007.

国内学会

  1. 山本 佳生, 定久 紀基, 金 多厚, 福田 駿 エリック, 浅井 哲也, 本村 真人, "頻出アイテムセットマイニング高速化のためのストリームプロセッサ," LSIとシステムのワークショップ, 北九州国際会議場, (北九州市), 2015年5月11-13日.
  2. 定久 紀基, 山本 佳生, 金 多厚, 福田 駿 エリック, 浅井 哲也, 本村 真人, "Locality-Sensitive HashingのスケーラブルなハードウェアアーキテクチャのFPGA実装," 電子情報通信学会総合大会, 立命館大学びわこ・くさつキャンパス, (草津), 2015年3月10-13日.
  3. 定久 紀基, 山本 佳生, 金 多厚, 福田 駿 エリック, 浅井 哲也, 本村 真人, "類似検索を行うLocality-Sensitive Hashingのスケーラブルなハードウェアアーキテクチャ," 電子情報通信学会集積回路研究会・コンピュータシステム研究会合同 平成26年度若手研究会, 機械振興会館, (東京), 2014年12月1-2日.
  4. 定久 紀基, 福田 駿 エリック, 浅井 哲也, 本村 真人, "実データ統計を用いた動的なMemcached評価用ロードジェネレータ," 電子情報通信学会総合大会, 新潟大学 五十嵐キャンパス, (新潟), 2014年3月18-21日.
  5. 福田 駿 エリック, 定久 紀基, 井上 浩明, 竹中 崇, 浅井 哲也, 本村 真人, "二重キャッシングによるMemcached高速化の提案," 電子情報通信学会 リコンフィギャラブルシステム研究会, 慶応義塾大学, (日吉), 2014年1月28-29日.
  6. 福田 駿 エリック, 川島 英之, 井上 浩明, 藤井 太郎, 古田 浩一朗, 浅井 哲也, 本村 真人, "リコンフィギュラブルハードウェアを用いた高速ストリーム処理の一検討," 電子情報通信学会 リコンフィギャラブルシステム研究会, 北陸先端科学技術大学院大学, (能美), 2013年9月18-19日.
  7. 福田 駿 エリック, 川島 英之, 井上 浩明, 浅井 哲也, 本村 真人, "C言語による動的リコンフィギュラブルハードウェアへのWindow Joinの実装," 電子情報通信学会 情報ネットワーク研究会, (福井), 2013年6月.
  8. 福田 駿 エリック, "自律的協調ロボットの集団形状化ルール：単純構造から超複雑構造の自己組織化へ向けて," データ駆動型生命情報科学の挑戦-スーパーコンピュータ「京」と生命情報科学の接点-, (仙台), 2012年5月.

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