Kaneko T., Orimo K., Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "A study on a low power optimization algorithm for an edge-AI Device," Nonlinear Theory and Its Applications, vol. E10-N, no. 4, pp. 373-389 (2019).
(研究紹介)百瀬 啓, 肥田 格, 浅井 哲也, "学習も推論も!人工知能スタータキット AI Arduino ーマイコンには荷が重すぎるニューラル・ネットワーク計算をFPGAで強力アシストー," トランジスタ技術, vol. 2018, no. 11, pp. 100-101 (2018).
Achararit P., Hida I., Marukame T., Asai T., and Hara-Azumi Y., "Structural exploration of stochastic neural networks for severely-constrained 3D memristive devices," Nonlinear Theory and Its Applications, vol. E9-N, no. 4, pp. 466-478 (2018).
Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "An energy-efficient dynamic branch predictor with a two-clock-cycle naive Bayes classifier for pipelined RISC microprocessors," Nonlinear Theory and Its Applications, vol. E8-N, no. 3, pp. 235-245 (2017).
Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "A high performance and energy efficient microprocessor with a novel restricted dynamically reconfigurable accelerator," Circuits and Systems, vol. 8, no. 5, pp. 134-147 (2017).
Kim D., Hida I., Fukuda E.S., Asai T., and Motomura M., "Reducing power and energy consumption of nonvolatile microcontrollers with transparent on-chip instruction cache," Circuits and Systems, vol. 5, no. 11, pp. 253-264 (2014).
Hida I., Ueyoshi K., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "Sign-invariant unsupervised learning facilitates weighted-sum computation in analog neural-network devices," 2017 International Symposium on Nonlinear Theory and Its Applications, Cancun International Convention Center, Cancun, Mexico (Dec. 4-7, 2017).
Hida I., Ikebe M., Asai T., and Motomura M., "A two-clock-cycle naive Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors," 2016 IEEE Asia Pacific Conference on Circuits and Systems, Ramada Plaza Jeju Hotel, Jeju, Korea (Oct. 25-28, 2016).
Hida I., Kim D., Asai T., and Motomura M., "A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator," Proceedings of the Asian Solid-State Circuits Conference 2014, pp. 37-40, 85 Sky Tower Hotel, KaoHsiung, Taiwan (Nov. 10-12, 2014).