Ou Y., Ambalathankandy P., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Real-time tone mapping: a survey and cross-implementation hardware benchmark," IEEE Transactions on Circuits and Systems for Video Technology, vol. 32, no. 5, pp. 2666-2686 (2022).
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Dither NN: hardware/algorithm co-design for accurate quantized neural networks," IEICE Transactions on Information and Systems, vol. E102, pp. 2341-2353 (2019).
Yamamoto K., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "FPGA-based annealing processor with time-division multiplexing," IEICE Transactions on Information and Systems, vol. E102-D, no. 12, pp. 2295-2305 (2019).
Kaneko T., Orimo K., Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "A study on a low power optimization algorithm for an edge-AI Device," Nonlinear Theory and Its Applications, vol. E10-N, no. 4, pp. 373-389 (2019).
Kaneko T., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Hardware-oriented algorithm and architecture for generative adversarial networks," Journal of Signal Processing, vol. 23, no. 4, pp. 151-154 (2019).
Hirose K., Uematsu R., Ando K., Ueyoshi K., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "Quantization error-based regularization for hardware-aware neural network training," Nonlinear Theory and Its Applications, vol. E9-N, no. 4, pp. 453-465 (2018).
Ambalathankandy P., Takamaeda-Yamazaki S., Motomura M., Asai T., Ikebe M., and Kusano H., "Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA," Microprocessors and Microsystems, vol. 61, pp. 21-31 (2018).
Ando K., Ueyoshi K., Orimo K., Yonekawa H., Sato S., Nakahara H., Takamaeda-Yamazaki S., Ikebe M., Asai T., Kuroda T., and Motomura M., "BRein memory: a single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4TOPS at 0.6W," IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 983-994 (2018).
Tanibata A., Schmid A., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "Proto-computing architecture over a digital medium aiming at real-time video processing," Complexity, vol. 2018, 3618621 (2018).
Tsuji T., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "6-DoF camera position and posture estimation based on local patches of image sequence," Journal of Signal Processing, vol. 21, no. 4, pp. 191-194 (2017).
Ando K., Takamaeda-Yamazaki S., Ikebe M., Asai T., and Motomura M., "A multithreaded CGRA for convolutional neural network processing," Circuits and Systems, vol. 8, no. 6, pp. 149-170 (2017).
Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "An energy-efficient dynamic branch predictor with a two-clock-cycle naive Bayes classifier for pipelined RISC microprocessors," Nonlinear Theory and Its Applications, vol. E8-N, no. 3, pp. 235-245 (2017).
Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "A high performance and energy efficient microprocessor with a novel restricted dynamically reconfigurable accelerator," Circuits and Systems, vol. 8, no. 5, pp. 134-147 (2017).
Yamamoto K., Ikebe M., Asai T., and Motomura M., "FPGA-based stream processing for frequent itemset mining with incremental multiple hashes," Circuits and Systems, vol. 7, no. 10, pp. 3299-3309 (2016).
Ikebe M., Uchida D., Take Y., Someya M., Chikuda S., Matsuyama K., Asai T., Kuroda T., and Motomura M., "3D stacked imager featuring inductive coupling channels for high speed/low-noise image transfer," ITE Transactions on Media Technology and Applications, vol. 4, no. 2, pp. 142-148 (2016).
Uchida D., Ikebe M., Motohisa J., and Sano E., "Low power single-slope ADC with intermittent-working time to digital converter," Journal of Signal Processing, vol. 19, no. 6, pp. 219-226 (2015).
Hiraishi K., Wada T., Kubo K., Otsu Y., Ikebe M., and Sano E., "Low-power, small-size transmitter module with metamaterial antenna," Analog Integrated Circuits and Signal Processing, vol. 83, no. 1, pp. 1-9 (2015).
Mori M., Itou T., Ikebe M., Asai T., Kuroda T., and Motomura M., "FPGA-based design for motion-vector estimation exploiting high-speed imaging and its application to motion classification with neural networks," Journal of Signal Processing, vol. 18, no. 4, pp. 165-168 (2014).
Uchida D., Ikebe M., Motohisa J., Sano E., and Kondou A., "CMOS common-mode rejection filter with floating active transformer operation," Japanese Journal of Applied Physics, vol. 53, no. 4S, pp. 04EE20-1-6 (2014).
(review) Ikebe M., "Recent progress in the technology linking sensors and digital circuits," IEICE Electronics Express, vol. 11, no. 3, pp. 1-13 (2014).
Sanada Y., Ohira T., Chikuda S., Igarashi M., Ikebe M., Asai T., and Motomura M., "FPGA implementation of single-image super resolution based on frame-bufferless box filtering," Journal of Signal Processing, vol. 17, no. 4, pp. 111-114 (2013).
Takahagi K., Matsushita H., Iida T., Ikebe M., Amemiya Y., and Sano E., "Low-power wake-up receiver with subthreshold CMOS circuits for wireless sensor networks," Analog Integrated Circuits and Signal Processing, vol. 75, no. 2, pp. 199-205 (2013).
Igarashi M., Ikebe M., Shimoyama S., and Motohisa J., "Fast bilateral filtering using recursive moving sum," Nonlinear Theory and Its Applications, vol. 3, no. 2, pp. 222-232 (2012).
Ikebe M. and Asai T., "A digital vision chip for early feature extraction with rotated template-matching cellular automata," Journal of Robotics and Mechatronics, vol. 17, no. 4, pp. 372-377 (2005).
Kagaya R., Ikebe M., Asai T., and Amemiya Y., "On-chip fixed-pattern-noise canceling with non-destructive intermediate readout circuitry for CMOS active-pixel sensors," WSEAS Transactions on Circuits and Systems, vol. 3, no. 3, pp. 477-479 (2004).
Kanazawa Y., Asai T., Ikebe M., and Amemiya Y., "A novel CMOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection," International Journal of Robotics and Automation, vol. 19, no. 4, pp. 206-212 (2004).
Oya T., Takahashi Y., Ikebe M., Asai T., and Amemiya Y., "A single-electron circuit as a discrete dynamical system," Superlattices and Microstructures, vol. 34, no. 3-6, pp. 253-258 (2003).
Asai T., Sunayama T., Amemiya Y., and Ikebe M., "A MOS vision chip based on the cellular-automaton processing," Japanese Journal of Applied Physics, vol. 40, no. 4B, pp. 2585-2592 (2001).
Sunayama T., Ikebe M., Asai T., and Amemiya Y., "Cellular νMOS circuits performing edge detection with difference-of-Gaussian Filters," Japanese Journal of Applied Physics, vol. 39, no. 4B, pp. 2278-2286 (2000).
Ikebe M., Akazawa M., and Amemiya Y., "A Functional nMOS circuit for implementing cellular-automaton picture-processing devices," Computers and Electrical Engineering, vol. 23, no. 6, pp. 439-451 (1997).
Ikebe M., Uchida D., Take Y., Asai T., Kuroda T., and Motomura M., "3D stacked image sensor featuring low noise inductive coupling channels," The 3rd International Workshop on Image Sensors and Imaging Systems, pp. 15-16, Tokyo Institute of Technology, Tokyo, Japan (Nov. 17-18, 2016).
Ambalathankandy P., Ou Y., Kochiyil J., Takamaeda-Yamazaki S., Motomura M., Asai T., and Ikebe M., "Radiography contrast enhancement: smoothed LHE filter, a practical solution for digital X-rays with Mach band," 2019 International Conference on Digital Image Computing: Techniques and Applications, University of Western Australia, Perth, Australia (Dec. 2-4, 2019).
Kaneko T., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Ternarized backpropagation: a hardware-oriented optimization algorithm for edge-oriented AI devices," The 7th RIEC International Symposium on Brain Functions and Brain Computer, Research Institute of Electrical Communication, Tohoku University, Sendai, Japan (Feb. 22-23, 2019).
Rim S., Suzuki S., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "Approach to reservoir computing with Schmitt trigger oscillator-based analog neural circuits," The 7th Japan-Korea Joint Workshop on Complex Communication Sciences, C5, Alpensia, Pyengonchang, Korea (Jan. 6-9, 2019).
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Dither NN: an accurate neural network with dithering for low bit-precision hardware," The 2018 International Conference on Field-Programmable Technology (FPT'18), Tenbusu-Naha Hall, Naha, Japan (Dec. 10-14, 2018).
Ambalathankandy P., Shimada T., Takamaeda-Yamazaki S., Motomura M., Asai T., and Ikebe M., "Analysis of smoothed LHE methods for processing images with optical illusions," IEEE International Conference on Visual Communications and Image Processing, Tempus Hotel Taichung , Taichung, Taiwan (Dec. 9-12, 2018).
Kudo T., Ueyoshi K., Ando K., Hirose K., Uematsu R., Oba Y., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "Area and energy optimization for bit-serial log-quantized DNN Accelerator with shared accumulators," IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, Vietnam National University, Hanoi, Vietnam (Sep. 12-14, 2018).
Shimada T., Ikebe M., Ambalathankandy P., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Sparse disparity estimation using global phase only correlation for stereo matching acceleration," 2018 IEEE International Conference on Acoustics, Speech and Signal Processing, Calgary Telus Convention Center, Alberta, Canada (Apr. 15-20, 2018).
Iwamaru N., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "A novel iris-center detection algorithm towards gaze estimation targeting molecular cellular automata," International Workshop on Molecular Architectonics 2018, P-25, Osaka University, Osaka, Japan (Mar. 2-3, 2018).
Hida I., Ueyoshi K., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "Sign-invariant unsupervised learning facilitates weighted-sum computation in analog neural-network devices," 2017 International Symposium on Nonlinear Theory and Its Applications, Cancun International Convention Center, Cancun, Mexico (Dec. 4-7, 2017).
Hirose K., Uematsu R., Ando K., Orimo K., Ueyoshi K., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Logarithmic Compression for Memory Footprint Reduction in Neural Network Training," 5th International Workshop on Computer Systems and Architectures (CSA 2017), Aomori Prefecture Tourist Center, Aomori, Japan (Nov. 19-22, 2017).
Tanibata A., Schmid A., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects (demo night)," The 27th International Conference on Field-Programmable Logic and Applications, Culture and Convention Center Het Pand, Ghent, Belgium (Sep. 4-8, 2017).
Ando K., Ueyoshi K., Hirose K., Orimo K., Yonekawa H., Sato S., Nakahara H., Ikebe M., Takamaeda-Yamazaki S., Asai T., Kuroda T., and Motomura M., "In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks," 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017), Tufts University, Boston, USA (Aug. 6-9, 2017).
Ando K., Ueyoshi K., Orimo K., Yonekawa H., Sato S., Nakahara H., Ikebe M., Asai T., Takamaeda-Yamazaki S., Kuroda T., and Motomura M., "BRein memory: a 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS," 2017 Symposia on VLSI Technology and Circuits, Rihga Royal Hotel, Kyoto, Japan (Jun. 5-8, 2017).
Ueyoshi K., Ando K., Orimo K., Ikebe M., Asai T., and Motomura M., "Exploring optimized accelerator design for binarized convolutional neural networks," The 2017 International Joint Conference on Neural Networks, William A. Egan Civic and Convention Center, Alaska, USA (May 14-19, 2017).
Yamamoto K., Takamaeda-Yamazaki S., Ikebe M., Asai T., and Motomura M., "A scalable ising model implementation on an FPGA," COOL Chips 20, Yokohama Media & Communications Center, Yokohama, Japan (Apr. 19-21, 2017).
Ando K., Ueyoshi K., Orimo K., Ikebe M., Takamaeda-Yamazaki S., Asai T., and Motomura M., "Throughput analysis of a data-flow reconfigurable array architecture for convolutional neural networks," The 5th RIEC International Symposium on Brain Functions and Brain Computer, Tohoku University, Sendai, Japan (Feb. 27-28, 2017).
Kusano H., Ikebe M., Asai T., and Motomura M., "An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions," 2016 International Conference on Reconfigurable Computing and FPGAs, Iberostar Cancun hotel, Cancun, Mexico (Nov. 30-Dec. 2, 2016).
Orimo K., Ando K., Ueyoshi K., Ikebe M., Asai T., and Motomura M., "FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting," 2016 International Conference on Reconfigurable Computing and FPGAs, Iberostar Cancun hotel, Cancun, Mexico (Nov. 30-Dec. 2, 2016).
Tanibata A., Ushida M., Schmid A., Ikebe M., Asai T., and Motomura M., "A hardware cellular-automaton architecture for spatial pattern generation towards motion-vector estimation of textureless objects," 2016 International Symposium on Nonlinear Theory and its Applications, pp. 622-625, New Welcity Yugawara, Shizuoka, Japan (Nov. 27-30, 2016).
Hida I., Ikebe M., Asai T., and Motomura M., "A two-clock-cycle naive Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors," 2016 IEEE Asia Pacific Conference on Circuits and Systems, Ramada Plaza Jeju Hotel, Jeju, Korea (Oct. 25-28, 2016).
Asai T., Mori M., Itou T., Take Y., Ikebe M., Kuroda T., and Motomura M., "Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces," European Solid-State Circuits Conference 2016, Swisstech Convention Centre, Lausanne, Switzerland (Sep. 12-15, 2016).
Ikebe M., Uchida D., Take Y., Someya M., Chikuda S., Matsuyama K., Asai T., Kuroda T., and Motomura M., "Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer," 2015 Symposia on VLSI Technology and Circuits, 4-1, Rihga Royal Hotel, Kyoto, Japan (Jun. 15-19, 2015).
Itou T., Mori M., Ikebe M., Asai T., Kuroda T., and Motomura M., "A new architecture for feature extraction to perform machine learning by using motion vectors and its implementation in an FPGA," Proceedings of the 2015 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, pp. 294-297, Universiti Teknologi Malaysia, Kuala Lumpur, Malaysia (Feb. 27-Mar. 2, 2015).
Mori M., Itou T., Ikebe M., Asai T., Kuroda T., and Motomura M., "FPGA-based design for motion-vector estimation exploiting high-speed imaging and its application to machine learning," Proceedings of the 2014 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, pp. 145-148, Waikiki Beach Marriott Resort & Spa, Honolulu, U.S.A. (Feb. 28-Mar. 3, 2014).
Sanada Y., Ohata K., Ogaki T., Matsuyama K., Ohira T., Chikuda S., Igarashi M., Kuroda T., Ikebe M., Asai T., and Motomura M., "FPGA implementation of a memory-efficient stereo vision algorithm based on 1-D guided filtering," Proceedings of the 2014 International Conference on Circuits, Systems, and Control, pp. 25-30, Lindner Grand Hotel Beau Rivage, Interlaken, Switzerland (Feb. 22-24, 2014).
Uchida D., Ikebe M., Someya M., and Motohisa J., "Low-power single-slope ADC with time to digital converter for CMOS image sensor," The 16th SNU-HU Joint Symposium, Seoul National University, Seoul, Korea (Dec. 13, 2013).
Ohata K., Sanada Y., Ogaki T., Matsuyama K., Ohira T., Chikuda S., Igarashi M., Ikebe M., Asai T., Motomura M., and Kuroda T., "Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation," Proceedings of the 2013 IEEE International Conference on Electronics, Circuits, and Systems, pp. 169-172, Yas Viceroy Hotel, Abu Dhabi, UAE (Dec. 8-11, 2013).
Chikuda S., Ohira T., Sanada Y., Igarashi M., Ikebe M., Asai T., and Motomura M., "FPGA implementation of 60-FPS QVGA-to-VGA single-image super resolution," in Proc. of the 2013 International Conference on Solid State Devices and Materials, pp. 136-137, Hilton Fukuoka Sea Hawk, Fukuoka, Japan (Sep. 24-27, 2013).
Sanada Y., Ohira T., Chikuda S., Igarashi M., Ikebe M., Asai T., and Motomura M., "FPGA implementation of single-image super resolution based on frame-bufferless box filtering," Proceedings of the 2013 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, pp. 516-519, Courtyard King Kamehameha's Kona Beach Hotel, The Island of Hawaii, U.S.A. (Mar. 4-7, 2013).
Asai T., Kanazawa Y., Ikebe M., and Amemiya Y., "A Neuromorphic CMOS Family and its Application," International Symposium on Bio-Inspired Systems, P8-5, Kitakyushu, Japan (Mar. 7-9, 2004).
Yamada T., Ikebe M., and Amemiya Y., "A current-mode νMOS circuit for cellular automaton devices," Proceedings of the International Symposium on Future of Intellectual Integrated Electronics, pp. 383-388, Sendai, Japan (Mar. 14-17, 1999).
Ikebe M. and Amemiya Y., "A νMOS cellular-automaton circuit for picture processing," Proceedings of the International Symposium on Future of Intellectual Integrated Electronics, pp. 377-382, Sendai, Japan (Mar. 14-17, 1999).
Rim S., Suzuki S., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "Approach to reservoir computing with Schmitt trigger oscillator-based analog neural circuits," JKCCS 2019 - Best Paper Award, Jan. 8, 2019.
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda S., and Motomura M., "Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware," FPT'18 - Best Paper Award, Dec. 13, 2018.