Suzuki J., Kaneko T., Ando K., Hirose K., Kawamura K., Chu T.V., Motomura M., and Yu J., "ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation," International Journal of Networking and Computing, vol. 11, no. 2, pp. 338-353 (2021).
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Dither NN: hardware/algorithm co-design for accurate quantized neural networks," IEICE Transactions on Information and Systems, vol. E102, pp. 2341-2353 (2019).
Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Hamada M., Kuroda T., and Motomura M., "QUEST: Multi-purpose log-quantized DNN inference engine stacked on 96-MB 3-D SRAM using inductive coupling technology in 40-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 186-196 (2019).
Hirose K., Uematsu R., Ando K., Ueyoshi K., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "Quantization error-based regularization for hardware-aware neural network training," Nonlinear Theory and Its Applications, vol. E9-N, no. 4, pp. 453-465 (2018).
国際会議
Okoshi Y., Lopez Garcia-Arias A., Hirose K., Ando K., Kawamura K., Chu T.V., Motomura M., and Yu J., "Multicoated Supermasks Enhance Hidden Networks," 39th International Conference on Machine Learning, Baltimore Convention Center, Baltimore, USA (Jul. 17-23, 2022).
Hirose K., Yu J., Ando K., Okoshi Y., Lopez Garcia-Arias A., Suzuki J., Chu T.V., Kawamura K., and Motomura M., "Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet," 2022 International Solid-State Circuits Conference (ISSCC 2022), Online, San Francisco, USA (Mar. 20-24, 2022).
Shiba K., Omori T., Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Motomura M., Hamada M., and Kuroda T., "A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Online, Seville, Spain (Oct. 10-21, 2020).
Suzuki J., Ando K., Hirose K., Kawamura K., Chu T.V., Motomura M., and Yu J., "ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation," 2020 Eighth International Symposium on Computing and Networking (CANDAR), Online, Naha, Japan (Sep. 24-27, 2020).
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Dither NN: an accurate neural network with dithering for low bit-precision hardware," The 2018 International Conference on Field-Programmable Technology (FPT'18), Tenbusu-Naha Hall, Naha, Japan (Dec. 10-14, 2018).
Kudo T., Ueyoshi K., Ando K., Hirose K., Uematsu R., Oba Y., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "Area and energy optimization for bit-serial log-quantized DNN Accelerator with shared accumulators," IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, Vietnam National University, Hanoi, Vietnam (Sep. 12-14, 2018).
Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Kadomoto J., Miyata T., Hamada M., Kuroda T., and Motomura M., "QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS," 2018 International Solid-State Circuits Conference (ISSCC 2018), San Francisco Marriott Marquis, San Francisco, US (Feb. 11-15, 2018).
Hirose K., Uematsu R., Ando K., Orimo K., Ueyoshi K., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Logarithmic Compression for Memory Footprint Reduction in Neural Network Training," 5th International Workshop on Computer Systems and Architectures (CSA 2017), Aomori Prefecture Tourist Center, Aomori, Japan (Nov. 19-22, 2017).
Ando K., Ueyoshi K., Hirose K., Orimo K., Yonekawa H., Sato S., Nakahara H., Ikebe M., Takamaeda-Yamazaki S., Asai T., Kuroda T., and Motomura M., "In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks," 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017), Tufts University, Boston, USA (Aug. 6-9, 2017).
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda S., and Motomura M., "Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware," FPT'18 - Best Paper Award, Dec. 13, 2018.
Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Kadomoto J., Miyata T., Hamada M., Kuroda T., and Motomura M., "QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS," ISSCC 2018 Silkroad Award, Feb. 11, 2018.