Kaneko T., Momose H., Suwa H., Ono T., Hayata Y., Kouno K., and Asai T., "On the control of computing-in-memory devices with resource-efficient digital circuits towards their on-chip learning," Nonlinear Theory and Its Applications, vol. E14-N, no. 4, pp. 639-651 (2023).
Yamagishi Y., Kaneko T., Akai-Kasaya M., and Asai T., "Holmes: A hardware-oriented optimizer using logarithms," IEICE Transactions on Information and Systems, vol. E105-D, no. 12, pp. 2040-2047 (2022).
Suzuki J., Kaneko T., Ando K., Hirose K., Kawamura K., Chu T.V., Motomura M., and Yu J., "ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation," International Journal of Networking and Computing, vol. 11, no. 2, pp. 338-353 (2021).
Yamagishi Y., Kaneko T., Akai-Kasaya M., and Asai T., "Hardware-oriented deep reinforcement learning for edge computing," Nonlinear Theory and Its Applications, vol. E12-N, no. 3, pp. 526-544 (2021).
Momose H., Kaneko T., and Asai T., "Systems and circuits for AI chips and their trends," Japanese Journal of Applied Physics, vol. 59, no. 5, 050502 (2020).
Kaneko T., Orimo K., Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "A study on a low power optimization algorithm for an edge-AI Device," Nonlinear Theory and Its Applications, vol. E10-N, no. 4, pp. 373-389 (2019).
Kaneko T., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Hardware-oriented algorithm and architecture for generative adversarial networks," Journal of Signal Processing, vol. 23, no. 4, pp. 151-154 (2019).
Kaneko T., Momose H., and Asai T., "On-Device Training Architecture for Analog ReRAM Neural Networks with Digital BP," MEMRISYS 2022, Boston Marriott Cambridge Cambridge, Cambridge, USA (Nov. 30-Dec. 2, 2022).
Kaneko T., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Ternarized backpropagation: a hardware-oriented optimization algorithm for edge-oriented AI devices," The 7th RIEC International Symposium on Brain Functions and Brain Computer, Research Institute of Electrical Communication, Tohoku University, Sendai, Japan (Feb. 22-23, 2019).