Yan J., Ando K., Yu J., and Motomura M., "TT-MLP: Tensor Train Decomposition on Deep MLPs," IEEE Access, vol. 11, pp. 10398-10411 (2023).
Jimbo S., Okonogi D., Ando K., Chu T.V., Yu J., Motomura M., and Kawamura K., "A Hybrid Integer Encoding Method for Obtaining High-quality Solutions of Quadratic Knapsack Problems on Solid-state Annealers," IEICE Transactions on Information and Systems, vol. E105-D, no. 12, pp. 2019-2031 (2022).
Ou Y., Ambalathankandy P., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Real-time tone mapping: a survey and cross-implementation hardware benchmark," IEEE Transactions on Circuits and Systems for Video Technology, vol. 32, no. 5, pp. 2666-2686 (2022).
Suzuki J., Kaneko T., Ando K., Hirose K., Kawamura K., Chu T.V., Motomura M., and Yu J., "ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation," International Journal of Networking and Computing, vol. 11, no. 2, pp. 338-353 (2021).
Yamamoto K., Kawamura K., Ando K., Mertig N., Takemoto T., Yamaoka M., Teramoto H., Sakai A., Takamaeda-Yamazaki S., and Motomura M., "STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin–Spin Interactions," IEEE Journal of Solid-State Circuits, vol. 56, no. 1, pp. 165-178 (2020).
Hirayama Y., Asai T., Motomura M., and Takamaeda-Yamazaki S., "A hardware-efficient weight sampling circuit for Bayesian neural networks," International Journal of Networking and Computing, vol. 10, no. 2, pp. 84-93 (2020).
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Dither NN: hardware/algorithm co-design for accurate quantized neural networks," IEICE Transactions on Information and Systems, vol. E102, pp. 2341-2353 (2019).
Yamamoto K., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "FPGA-based annealing processor with time-division multiplexing," IEICE Transactions on Information and Systems, vol. E102-D, no. 12, pp. 2295-2305 (2019).
Kaneko T., Orimo K., Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "A study on a low power optimization algorithm for an edge-AI Device," Nonlinear Theory and Its Applications, vol. E10-N, no. 4, pp. 373-389 (2019).
Kaneko T., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Hardware-oriented algorithm and architecture for generative adversarial networks," Journal of Signal Processing, vol. 23, no. 4, pp. 151-154 (2019).
Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Hamada M., Kuroda T., and Motomura M., "QUEST: Multi-purpose log-quantized DNN inference engine stacked on 96-MB 3-D SRAM using inductive coupling technology in 40-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 186-196 (2019).
Hirose K., Uematsu R., Ando K., Ueyoshi K., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "Quantization error-based regularization for hardware-aware neural network training," Nonlinear Theory and Its Applications, vol. E9-N, no. 4, pp. 453-465 (2018).
Ambalathankandy P., Takamaeda-Yamazaki S., Motomura M., Asai T., Ikebe M., and Kusano H., "Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA," Microprocessors and Microsystems, vol. 61, pp. 21-31 (2018).
Ando K., Ueyoshi K., Orimo K., Yonekawa H., Sato S., Nakahara H., Takamaeda-Yamazaki S., Ikebe M., Asai T., Kuroda T., and Motomura M., "BRein memory: a single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4TOPS at 0.6W," IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 983-994 (2018).
Tanibata A., Schmid A., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "Proto-computing architecture over a digital medium aiming at real-time video processing," Complexity, vol. 2018, 3618621 (2018).
Tsuji T., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "6-DoF camera position and posture estimation based on local patches of image sequence," Journal of Signal Processing, vol. 21, no. 4, pp. 191-194 (2017).
Ando K., Takamaeda-Yamazaki S., Ikebe M., Asai T., and Motomura M., "A multithreaded CGRA for convolutional neural network processing," Circuits and Systems, vol. 8, no. 6, pp. 149-170 (2017).
Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "An energy-efficient dynamic branch predictor with a two-clock-cycle naive Bayes classifier for pipelined RISC microprocessors," Nonlinear Theory and Its Applications, vol. E8-N, no. 3, pp. 235-245 (2017).
Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "A high performance and energy efficient microprocessor with a novel restricted dynamically reconfigurable accelerator," Circuits and Systems, vol. 8, no. 5, pp. 134-147 (2017).
Marukame T., Ueyoshi K., Asai T., Motomura M., Schmid A., Suzuki M., Higashi Y., and Mitani Y., "Error tolerance analysis of deep learning hardware using restricted Boltzmann machine towards low-power memory implementation," IEEE Transactions on Circuits and Systems II, vol. 64, no. 4, pp. 462-466 (2017).
Yamamoto K., Ikebe M., Asai T., and Motomura M., "FPGA-based stream processing for frequent itemset mining with incremental multiple hashes," Circuits and Systems, vol. 7, no. 10, pp. 3299-3309 (2016).
Ueyoshi K., Marukame T., Asai T., Motomura M., and Schmid A., "FPGA implementation of a scalable and highly parallel architecture for restricted Boltzmann machines," Circuits and Systems, vol. 7, no. 9, pp. 2132-2141 (2016).
Ueyoshi K., Marukame T., Asai T., Motomura M., and Schmid A., "Robustness of hardware-oriented restricted Boltzmann machines in deep belief networks for reliable processing," Nonlinear Theory and Its Applications, vol. E7-N, no. 3, pp. 395-406 (2016).
Ushida M., Schmid A., Asai T., Ishimura K., and Motomura M., "Motion vector estimation of textureless objects exploiting reaction-diffusion cellular automata," International Journal of Unconventional Computing, vol. 12, no. 2-3, pp. 169-187 (2016).
Ishimura K., Schmid A., Asai T., and Motomura M., "Stochastic resonance induced by internal noise in a unidirectional network of excitable FitzHugh-Nagumo neurons," Nonlinear Theory and Its Applications, vol. 7, no. 2, pp. 164-175 (2016).
Ikebe M., Uchida D., Take Y., Someya M., Chikuda S., Matsuyama K., Asai T., Kuroda T., and Motomura M., "3D stacked imager featuring inductive coupling channels for high speed/low-noise image transfer," ITE Transactions on Media Technology and Applications, vol. 4, no. 2, pp. 142-148 (2016).
El-Sankary K., Asai T., Kuroda T., and Motomura M., "Crosstalk rejection in 3D-stacked inter-chip communication with blind source separation," IEEE Transactions on Circuits and Systems II, vol. 62, no. 8, pp. 726-730 (2015).
Ishimura K., Komuro K., Schmid A., Asai T., and Motomura M., "FPGA implementation of hardware-oriented reaction-diffusion cellular automata models," Nonlinear Theory and Its Applications, vol. 6, no. 2, pp. 252-262 (2015).
Hsu L.-C., Motomura M., Take Y., and Kuroda T., "Through chip interface based three-dimensional FPGA architecture exploration," IEICE Transactions on Electronics, vol. E98-C, no. 4, pp. 288-297 (2015).
Fukuda E.S., Inoue H., Takenaka T., Kim D., Sadahisa T., Asai T., and Motomura M., "Enhancing memcached by caching its data and functionalities at network interface," IPSJ Journal, vol. 56, no. 3, pp. 143-152 (2015).
Kim D., Hida I., Fukuda E.S., Asai T., and Motomura M., "Reducing power and energy consumption of nonvolatile microcontrollers with transparent on-chip instruction cache," Circuits and Systems, vol. 5, no. 11, pp. 253-264 (2014).
Gonzalez-Carabarin L., Asai T., and Motomura M., "Application of nonlinear systems for designing low-power logic gates based on stochastic resonance," Nonlinear Theory and Its Applications, vol. 5, no. 4, pp. 445-455 (2014).
Ishimura K., Komuro K., Schmid A., Asai T., and Motomura M., "Image steganography based on reaction diffusion models toward hardware implementation," Nonlinear Theory and Its Applications, vol. 5, no. 4, pp. 456-465 (2014).
Mori M., Itou T., Ikebe M., Asai T., Kuroda T., and Motomura M., "FPGA-based design for motion-vector estimation exploiting high-speed imaging and its application to motion classification with neural networks," Journal of Signal Processing, vol. 18, no. 4, pp. 165-168 (2014).
Gonzalez-Carabarin L., Asai T., and Motomura M., "Low-power asynchronous digital pipeline based on mismatch-tolerant logic gates," IEICE Electronics Express, vol. 11, no. 15, pp. 20140632/1-9 (2014).
Ishimura K., Asai T., and Motomura M., "Chaotic resonance in forced Chua's oscillators," Journal of Signal Processing, vol. 17, no. 6, pp. 231-238 (2013).
Fukuda E.S., Kawashima H., Inoue H., Asai T., and Motomura M., "C-based design of window join for dynamically reconfigurable hardware," Journal of Computer Science and Engineering, vol. 20, no. 2, pp. 1-9 (2013).
Sanada Y., Ohira T., Chikuda S., Igarashi M., Ikebe M., Asai T., and Motomura M., "FPGA implementation of single-image super resolution based on frame-bufferless box filtering," Journal of Signal Processing, vol. 17, no. 4, pp. 111-114 (2013).
Gong X., Asai T., and Motomura M., "Excitable reaction-diffusion media with memristors," Journal of Signal Processing, vol. 16, no. 4, pp. 283-286 (2012).
Matsuura M., Asai T., and Motomura M., "Noise-induced phase synchronization among simple digital counters," Journal of Signal Processing, vol. 16, no. 4, pp. 279-282 (2012).
Gonzalez-Carabarin L., Asai T., and Motomura M., "Impact of noise on spike transmission through serially-connected electrical FitzHugh-Nagumo circuits with subthreshold and suprathreshold interconductances," Journal of Signal Processing, vol. 16, no. 6, pp. 503-509 (2012).
Inoue H., Takenaka T., and Motomura M., "Hardware design for C-based complex event processing," Embedded Systems Design with FPGAs, Athanas P., Pnevmatikatos D., and Sklavos N., Eds., chapter 4, pp. 79-100, Springer Verlag (2012).
Motomura M., "Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures," International IoT Solid-State Circuits Workshop, National Nano Device Laboratories, Hshinchu, Taiwan (Nov. 9, 2018).
Motomura M., "Trends toward Reconfigurable and in-Memory Processing Architectures for Deep Neural Networks," Future Chips 2017, Tsinghua University, Beijing, China (Dec. 20, 2017).
本村 真人, "機械学習向けチップの動向," ISSCC2018記者会見, 経団連会館, Tokyo, Japan (Nov. 13, 2017).
Motomura M., "Research Activity on Deep Neural Network Accelerators," Tsinghua University Workshop, Chinese Science Academy, Beijin, China (Oct. 31, 2017).
Motomura M., "A Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator," CSAIL Seminor, MIT, Cambridge, USA (Aug. 9, 2017).
Motomura M., "A Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator," SEAS Seminor, Harvard University, Cambridge, USA (Aug. 8, 2017).
本村 真人, "AI応用が導く情報処理ハードウェアの革新," Impactセミナー, 経団連会館, Tokyo, Japan (Jul. 12, 2017).
本村 真人, "AI応用が導く情報処理ハードウェアの革新," Impulseコンソーシアムセミナー, アキバプラザ, Tokyo, Japan (Jul. 12, 2017).
Motomura M., "Rise of deep neural network accelerators ," Workshop on Brain-inspired Hardware, AIST Tokyo waterfront Annex building, Tokyo, Japan (Mar. 30, 2017).
Ikebe M., Uchida D., Take Y., Asai T., Kuroda T., and Motomura M., "3D stacked image sensor featuring low noise inductive coupling channels," The 3rd International Workshop on Image Sensors and Imaging Systems, pp. 15-16, Tokyo Institute of Technology, Tokyo, Japan (Nov. 17-18, 2016).
本村 真人, "2014 Symposium on VLSI Circuits採択論文に見る最新技術トレンド," LSIとシステムのワークショップ2014, Kitakyushu International Conference Center, Kokura, Japan (May 26-28, 2014).
福田 駿 エリック, 本村 真人, "ソフトウェア記述によるハードウェアストリーム処理," 2013年度筑波大学DB meets FPGAセミナー, University of Tsukuba, Tsukuba, Japan (Apr. 26, 2013).
Suzuki J., Yu J., Yasunaga M., Lopez Garcia-Arias A., Okoshi Y., Kumazawa S., Ando K., Kawamura K., Chu T.V., and Motomura M., "Pianissimo: A sub-mW class DNN accelerator with progressive bit-by-bit datapath architecture for adaptive inference at edge," 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Rihga Royal Hotel Kyoto, Kyoto, Japan (Jun. 11-16, 2023).
Kawamura K., Yu J., Okonogi D., Jimbo S., Inoue G., Hyodo A., Lopez Garcia-Arias A., Ando K., Fukushima-Kimura B.H., Yasudo R., Chu T.V., and Motomura M., "Amorphica: 4-replica 512 fully connected spin 336MHz metamorphic annealer with programmable optimization strategy and compressed-spin-transfer multi-chip extension," 2023 International Solid-State Circuits Conference (ISSCC 2023), San Francisco Marriott Marquis, San Francisco, US (Feb. 19-23, 2023).
Okoshi Y., Lopez Garcia-Arias A., Hirose K., Ando K., Kawamura K., Chu T.V., Motomura M., and Yu J., "Multicoated Supermasks Enhance Hidden Networks," 39th International Conference on Machine Learning, Baltimore Convention Center, Baltimore, USA (Jul. 17-23, 2022).
Hirose K., Yu J., Ando K., Okoshi Y., Lopez Garcia-Arias A., Suzuki J., Chu T.V., Kawamura K., and Motomura M., "Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet," 2022 International Solid-State Circuits Conference (ISSCC 2022), Online, San Francisco, USA (Mar. 20-24, 2022).
Ando K., Yu J., Hirose M., Nakahara H., Kawamura K., Chu T.V., and Motomura M., "Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner," 2021 IEEE Hot Chips 33 Symposium, Online, Palo Alto, USA (Aug. 22-24, 2021).
Shiba K., Omori T., Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Motomura M., Hamada M., and Kuroda T., "A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Online, Seville, Spain (Oct. 10-21, 2020).
Suzuki J., Ando K., Hirose K., Kawamura K., Chu T.V., Motomura M., and Yu J., "ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation," 2020 Eighth International Symposium on Computing and Networking (CANDAR), Online, Naha, Japan (Sep. 24-27, 2020).
Yamamoto K., Ando K., Mertig N., Takemoto T., Yamaoka M., Teramoto H., Sakai A., Takamaeda-Yamazaki S., and Motomura M., "STATICA: A 512-spin 0.25M-weight full-digital annealing processor with a near-memory all-spin-updates-at-once architecture for combinatorial optimization with complete spin-spin interactions," 2020 International Solid-State Circuits Conference (ISSCC 2020), San Francisco Marriott Marquis, San Francisco, USA (Feb. 16-20, 2020).
Ambalathankandy P., Ou Y., Kochiyil J., Takamaeda-Yamazaki S., Motomura M., Asai T., and Ikebe M., "Radiography contrast enhancement: smoothed LHE filter, a practical solution for digital X-rays with Mach band," 2019 International Conference on Digital Image Computing: Techniques and Applications, University of Western Australia, Perth, Australia (Dec. 2-4, 2019).
Kaneko T., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Ternarized backpropagation: a hardware-oriented optimization algorithm for edge-oriented AI devices," The 7th RIEC International Symposium on Brain Functions and Brain Computer, Research Institute of Electrical Communication, Tohoku University, Sendai, Japan (Feb. 22-23, 2019).
Rim S., Suzuki S., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "Approach to reservoir computing with Schmitt trigger oscillator-based analog neural circuits," The 7th Japan-Korea Joint Workshop on Complex Communication Sciences, C5, Alpensia, Pyengonchang, Korea (Jan. 6-9, 2019).
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Dither NN: an accurate neural network with dithering for low bit-precision hardware," The 2018 International Conference on Field-Programmable Technology (FPT'18), Tenbusu-Naha Hall, Naha, Japan (Dec. 10-14, 2018).
Ambalathankandy P., Shimada T., Takamaeda-Yamazaki S., Motomura M., Asai T., and Ikebe M., "Analysis of smoothed LHE methods for processing images with optical illusions," IEEE International Conference on Visual Communications and Image Processing, Tempus Hotel Taichung , Taichung, Taiwan (Dec. 9-12, 2018).
Kudo T., Ueyoshi K., Ando K., Hirose K., Uematsu R., Oba Y., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "Area and energy optimization for bit-serial log-quantized DNN Accelerator with shared accumulators," IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, Vietnam National University, Hanoi, Vietnam (Sep. 12-14, 2018).
Fujii T., Toi T., Tanaka T., Togawa K., Kitaoka T., Nishino K., Nakamura N., Nakahara H., and Motomura M., "New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications," 2018 Symposia on VLSI Technology and Circuits, pp. 41-42, Hilton Hawaiian Village, Hawaii, USA (Jun. 19-21, 2018).
Shimada T., Ikebe M., Ambalathankandy P., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Sparse disparity estimation using global phase only correlation for stereo matching acceleration," 2018 IEEE International Conference on Acoustics, Speech and Signal Processing, Calgary Telus Convention Center, Alberta, Canada (Apr. 15-20, 2018).
Iwamaru N., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "A novel iris-center detection algorithm towards gaze estimation targeting molecular cellular automata," International Workshop on Molecular Architectonics 2018, P-25, Osaka University, Osaka, Japan (Mar. 2-3, 2018).
Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Kadomoto J., Miyata T., Hamada M., Kuroda T., and Motomura M., "QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS," 2018 International Solid-State Circuits Conference (ISSCC 2018), San Francisco Marriott Marquis, San Francisco, US (Feb. 11-15, 2018).
Hida I., Ueyoshi K., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "Sign-invariant unsupervised learning facilitates weighted-sum computation in analog neural-network devices," 2017 International Symposium on Nonlinear Theory and Its Applications, Cancun International Convention Center, Cancun, Mexico (Dec. 4-7, 2017).
Hirose K., Uematsu R., Ando K., Orimo K., Ueyoshi K., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Logarithmic Compression for Memory Footprint Reduction in Neural Network Training," 5th International Workshop on Computer Systems and Architectures (CSA 2017), Aomori Prefecture Tourist Center, Aomori, Japan (Nov. 19-22, 2017).
Tanibata A., Schmid A., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects (demo night)," The 27th International Conference on Field-Programmable Logic and Applications, Culture and Convention Center Het Pand, Ghent, Belgium (Sep. 4-8, 2017).
Ando K., Ueyoshi K., Hirose K., Orimo K., Yonekawa H., Sato S., Nakahara H., Ikebe M., Takamaeda-Yamazaki S., Asai T., Kuroda T., and Motomura M., "In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks," 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017), Tufts University, Boston, USA (Aug. 6-9, 2017).
Ando K., Ueyoshi K., Orimo K., Yonekawa H., Sato S., Nakahara H., Ikebe M., Asai T., Takamaeda-Yamazaki S., Kuroda T., and Motomura M., "BRein memory: a 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS," 2017 Symposia on VLSI Technology and Circuits, Rihga Royal Hotel, Kyoto, Japan (Jun. 5-8, 2017).
Ueyoshi K., Marukame T., Asai T., Motomura M., and Schmid A., "Feature extraction system using restricted Boltzmann machines on FPGA," 2017 IEEE International Symposium on Circuits & Systems, A4P-O, Baltimore Marriott Waterfront, Baltimore, USA (May 28-31, 2017).
Ueyoshi K., Ando K., Orimo K., Ikebe M., Asai T., and Motomura M., "Exploring optimized accelerator design for binarized convolutional neural networks," The 2017 International Joint Conference on Neural Networks, William A. Egan Civic and Convention Center, Alaska, USA (May 14-19, 2017).
Yamamoto K., Takamaeda-Yamazaki S., Ikebe M., Asai T., and Motomura M., "A scalable ising model implementation on an FPGA," COOL Chips 20, Yokohama Media & Communications Center, Yokohama, Japan (Apr. 19-21, 2017).
Fujii T., Sato S., Nakahara H., and Motomura M., "An FPGA realization of a deep convolutional neural network using a threshold neuron pruning," International Symposium on Applied Reconfigurable Computing, Delft University, Delft, Netherlands (Apr. 3-7, 2017).
Ando K., Ueyoshi K., Orimo K., Ikebe M., Takamaeda-Yamazaki S., Asai T., and Motomura M., "Throughput analysis of a data-flow reconfigurable array architecture for convolutional neural networks," The 5th RIEC International Symposium on Brain Functions and Brain Computer, Tohoku University, Sendai, Japan (Feb. 27-28, 2017).
Nakahara H., Yonekawa H., Iwamoto H., and Motomura M., "A batch normalization free binarized convolutional deep neural network on an FPGA," International Symposium on Field-Programmable Gate Array, Monterey Marriott Hotel, California, USA (Feb. 22-24, 2017).
Nakahara H., Yonekawa H., Sasao T., Iwamoto H., and Motomura M., "A memory-based realization of a binarized deep convolutional neural network," International Conference on Field-Programmable Technology, Jiangou Hotel, Xi'an, China (Dec. 7-9, 2016).
Kusano H., Ikebe M., Asai T., and Motomura M., "An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions," 2016 International Conference on Reconfigurable Computing and FPGAs, Iberostar Cancun hotel, Cancun, Mexico (Nov. 30-Dec. 2, 2016).
Orimo K., Ando K., Ueyoshi K., Ikebe M., Asai T., and Motomura M., "FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting," 2016 International Conference on Reconfigurable Computing and FPGAs, Iberostar Cancun hotel, Cancun, Mexico (Nov. 30-Dec. 2, 2016).
Tanibata A., Ushida M., Schmid A., Ikebe M., Asai T., and Motomura M., "A hardware cellular-automaton architecture for spatial pattern generation towards motion-vector estimation of textureless objects," 2016 International Symposium on Nonlinear Theory and its Applications, pp. 622-625, New Welcity Yugawara, Shizuoka, Japan (Nov. 27-30, 2016).
Hida I., Ikebe M., Asai T., and Motomura M., "A two-clock-cycle naive Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors," 2016 IEEE Asia Pacific Conference on Circuits and Systems, Ramada Plaza Jeju Hotel, Jeju, Korea (Oct. 25-28, 2016).
Asai T., Mori M., Itou T., Take Y., Ikebe M., Kuroda T., and Motomura M., "Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces," European Solid-State Circuits Conference 2016, Swisstech Convention Centre, Lausanne, Switzerland (Sep. 12-15, 2016).
Ueyoshi K., Marukame T., Asai T., Motomura M., and Schmid A., "Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in deep belief network," IEEE International Symposium on Circuits and Systems, Montreal Sheraton Center, Montreal, Canada (May 22-25, 2016).
Yamamoto K., Asai T., and Motomura M., "Hardware architecture for online frequent items mining with memory-efficient data structure," COOL Chips XIX, Yokohama Media & Communications Center, Yokohama, Japan (Apr. 20-22, 2016).
Ushida M., Ishimura K., Schmid A., Asai T., and Motomura M., "Motion vector estimation of textureless objects exploiting reaction-diffusion cellular automata," 2015 International Symposium on Nonlinear Theory and its Applications, pp. 85-88, City University of Hong Kong, Hong Kong, China (Dec. 1-4, 2015).
Ikebe M., Uchida D., Take Y., Someya M., Chikuda S., Matsuyama K., Asai T., Kuroda T., and Motomura M., "Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer," 2015 Symposia on VLSI Technology and Circuits, 4-1, Rihga Royal Hotel, Kyoto, Japan (Jun. 15-19, 2015).
Itou T., Mori M., Ikebe M., Asai T., Kuroda T., and Motomura M., "A new architecture for feature extraction to perform machine learning by using motion vectors and its implementation in an FPGA," Proceedings of the 2015 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, pp. 294-297, Universiti Teknologi Malaysia, Kuala Lumpur, Malaysia (Feb. 27-Mar. 2, 2015).
Fukuda E.S., Inoue H., Takenaka T., Kim D., Sadahisa T., Asai T., and Motomura M., "Achieving higher performance of memcached by caching at network interface," The 2014 International Conference on Field Programmable Technology, Parkyard Hotel, Shanghai, China (Dec. 10-12, 2014).
Hida I., Kim D., Asai T., and Motomura M., "A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator," Proceedings of the Asian Solid-State Circuits Conference 2014, pp. 37-40, 85 Sky Tower Hotel, KaoHsiung, Taiwan (Nov. 10-12, 2014).
Kim D., Fukuda E.S., Sadahisa T., Asai T., and Motomura M., "Hardware architecture for accelerating key-value retrieval implemented on FPGA," The 3rd Japan-Korea Joint Workshop on Complex Communication Sciences, Paradise Hotel, Busan, Korea (Oct. 27-28, 2014).
Gonzalez-Carabarin L., Asai T., and Motomura M., "Dual-rail asynchronous pipeline based on stochastic resonance logic gates," Proceedings of the 2014 International Symposium on Nonlinear Theory and its Applications, pp. 85-88, Cinema of Bourbaki Panorama, Luzern, Switzerland (Sep. 14-18, 2014).
Ishimura K., Komuro K., Schmid A., Asai T., and Motomura M., "Stochastic resonance in a unidirectional network of nonlinear oscillators driven by internal noise," Proceedings of the 2014 International Symposium on Nonlinear Theory and its Applications, pp. 89-92, Cinema of Bourbaki Panorama, Luzern, Switzerland (Sep. 14-18, 2014).
Mori M., Itou T., Ikebe M., Asai T., Kuroda T., and Motomura M., "FPGA-based design for motion-vector estimation exploiting high-speed imaging and its application to machine learning," Proceedings of the 2014 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, pp. 145-148, Waikiki Beach Marriott Resort & Spa, Honolulu, U.S.A. (Feb. 28-Mar. 3, 2014).
Sanada Y., Ohata K., Ogaki T., Matsuyama K., Ohira T., Chikuda S., Igarashi M., Kuroda T., Ikebe M., Asai T., and Motomura M., "FPGA implementation of a memory-efficient stereo vision algorithm based on 1-D guided filtering," Proceedings of the 2014 International Conference on Circuits, Systems, and Control, pp. 25-30, Lindner Grand Hotel Beau Rivage, Interlaken, Switzerland (Feb. 22-24, 2014).
Ohata K., Sanada Y., Ogaki T., Matsuyama K., Ohira T., Chikuda S., Igarashi M., Ikebe M., Asai T., Motomura M., and Kuroda T., "Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation," Proceedings of the 2013 IEEE International Conference on Electronics, Circuits, and Systems, pp. 169-172, Yas Viceroy Hotel, Abu Dhabi, UAE (Dec. 8-11, 2013).
Fukuda E.S., Takenaka T., Inoue H., Kawashima H., Asai T., and Motomura M., "High level synthesis with stream query to C parser: Eliminating hardware development difficulties for software developers," Proceedings of the 18th Workshop on Synthesis And System Integration of Mixed Information Technologies, pp. 310-315, Hotel Sapporo Garden Palace, Sapporo, Japan (Oct. 21-22, 2013).
Chikuda S., Ohira T., Sanada Y., Igarashi M., Ikebe M., Asai T., and Motomura M., "FPGA implementation of 60-FPS QVGA-to-VGA single-image super resolution," in Proc. of the 2013 International Conference on Solid State Devices and Materials, pp. 136-137, Hilton Fukuoka Sea Hawk, Fukuoka, Japan (Sep. 24-27, 2013).
Gonzalez-Carabarin L., Asai T., and Motomura M., "Towards asynchronous digital circuit design based on stochastic resonance," The 1st International Conference on Nanoenergy, Hotel Gio, Perugia, Italy (Jul. 10-13, 2013).
Ishimura K., Schmid A., Asai T., and Motomura M., "Image steganography on digital reaction-diffusion processor," Nonlinear Dynamics of Electronic Systems 2013, Palazzo Ateneo, Bari, Italy (Jul. 10-12, 2013).
Fukuda E.S., Kawashima H., Inoue H., Fujii T., Furuta K., Asai T., and Motomura M., "C-based adaptive stream processing on dynamically reconfigurable hardware: window join case study," The 9th International Symposium on Applied Reconfigurable Computing, Courtyard Marriott Los Angeles, Los Angeles, U.S.A. (Mar. 25-27, 2013).
Sanada Y., Ohira T., Chikuda S., Igarashi M., Ikebe M., Asai T., and Motomura M., "FPGA implementation of single-image super resolution based on frame-bufferless box filtering," Proceedings of the 2013 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, pp. 516-519, Courtyard King Kamehameha's Kona Beach Hotel, The Island of Hawaii, U.S.A. (Mar. 4-7, 2013).
Gonzalez-Carabarin L., Asai T., and Motomura M., "Spike transmission in locally coupled excitable circuits enhanced by membrane-potential-dependent noise," Asia Conference on Nanoscience and Nanotechnology 2012, Crowne Plaza Lijiang Ancient Town, Yunnan, China (Sep. 7-10, 2012).
Gong X., Asai T., and Motomura M., "Spatio-temporal pattern formation on memristive reaction-diffusion systems," Asia Conference on Nanoscience and Nanotechnology 2012, Crowne Plaza Lijiang Ancient Town, Yunnan, China (Sep. 7-10, 2012).
Gonzalez-Carabarin L., Asai T., and Motomura M., "Noise impact on spike transmission through serially-connected electrical FitzHugh-Nagumo model with subthreshold and suprathreshold interconductances," The 16th International Conference On Cognitive and Neural Systems, Boston University, Boston, U.S.A. (May 30-Jun. 1, 2012).
Yoshida K., Asai T., and Motomura M., "A subthreshold memory cell utilizing nonlinear characteristics of positive-feedback operational transconductance amplifier," Proceedings of the 2011 Kyoto Workshop on NOLTA, p. 15, Kyoto University, Kyoto, Japan (Nov. 30, 2011).
Toi T., Awashima T., Motomura M., and Amano H., "Time and space-multiplexed compilation challenge for dynamically reconfigurable processors," Proceesings of the 54th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), P03_1039, Yonsei University Seoul, Seoul, Korea (Aug. 7-10, 2011).
Rim S., Suzuki S., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "Approach to reservoir computing with Schmitt trigger oscillator-based analog neural circuits," JKCCS 2019 - Best Paper Award, Jan. 8, 2019.
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda S., and Motomura M., "Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware," FPT'18 - Best Paper Award, Dec. 13, 2018.
Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Kadomoto J., Miyata T., Hamada M., Kuroda T., and Motomura M., "QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS," ISSCC 2018 Silkroad Award, Feb. 11, 2018.