Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Dither NN: hardware/algorithm co-design for accurate quantized neural networks," IEICE Transactions on Information and Systems, vol. E102, pp. 2341-2353 (2019).
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Dither NN: an accurate neural network with dithering for low bit-precision hardware," The 2018 International Conference on Field-Programmable Technology (FPT'18), Tenbusu-Naha Hall, Naha, Japan (Dec. 10-14, 2018).
Kudo T., Ueyoshi K., Ando K., Hirose K., Uematsu R., Oba Y., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "Area and energy optimization for bit-serial log-quantized DNN Accelerator with shared accumulators," IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, Vietnam National University, Hanoi, Vietnam (Sep. 12-14, 2018).
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda S., and Motomura M., "Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware," FPT'18 - Best Paper Award, Dec. 13, 2018.