Ou Y., Ambalathankandy P., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Real-time tone mapping: a survey and cross-implementation hardware benchmark," IEEE Transactions on Circuits and Systems for Video Technology, vol. 32, no. 5, pp. 2666-2686 (2022).
Yamamoto K., Kawamura K., Ando K., Mertig N., Takemoto T., Yamaoka M., Teramoto H., Sakai A., Takamaeda-Yamazaki S., and Motomura M., "STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin–Spin Interactions," IEEE Journal of Solid-State Circuits, vol. 56, no. 1, pp. 165-178 (2020).
Hirayama Y., Asai T., Motomura M., and Takamaeda-Yamazaki S., "A hardware-efficient weight sampling circuit for Bayesian neural networks," International Journal of Networking and Computing, vol. 10, no. 2, pp. 84-93 (2020).
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Dither NN: hardware/algorithm co-design for accurate quantized neural networks," IEICE Transactions on Information and Systems, vol. E102, pp. 2341-2353 (2019).
Yamamoto K., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "FPGA-based annealing processor with time-division multiplexing," IEICE Transactions on Information and Systems, vol. E102-D, no. 12, pp. 2295-2305 (2019).
Kaneko T., Orimo K., Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "A study on a low power optimization algorithm for an edge-AI Device," Nonlinear Theory and Its Applications, vol. E10-N, no. 4, pp. 373-389 (2019).
Kaneko T., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Hardware-oriented algorithm and architecture for generative adversarial networks," Journal of Signal Processing, vol. 23, no. 4, pp. 151-154 (2019).
Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Hamada M., Kuroda T., and Motomura M., "QUEST: Multi-purpose log-quantized DNN inference engine stacked on 96-MB 3-D SRAM using inductive coupling technology in 40-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 186-196 (2019).
Hirose K., Uematsu R., Ando K., Ueyoshi K., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "Quantization error-based regularization for hardware-aware neural network training," Nonlinear Theory and Its Applications, vol. E9-N, no. 4, pp. 453-465 (2018).
Ambalathankandy P., Takamaeda-Yamazaki S., Motomura M., Asai T., Ikebe M., and Kusano H., "Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA," Microprocessors and Microsystems, vol. 61, pp. 21-31 (2018).
Ando K., Ueyoshi K., Orimo K., Yonekawa H., Sato S., Nakahara H., Takamaeda-Yamazaki S., Ikebe M., Asai T., Kuroda T., and Motomura M., "BRein memory: a single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4TOPS at 0.6W," IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 983-994 (2018).
Tanibata A., Schmid A., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "Proto-computing architecture over a digital medium aiming at real-time video processing," Complexity, vol. 2018, 3618621 (2018).
Tsuji T., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "6-DoF camera position and posture estimation based on local patches of image sequence," Journal of Signal Processing, vol. 21, no. 4, pp. 191-194 (2017).
Ando K., Takamaeda-Yamazaki S., Ikebe M., Asai T., and Motomura M., "A multithreaded CGRA for convolutional neural network processing," Circuits and Systems, vol. 8, no. 6, pp. 149-170 (2017).
Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "An energy-efficient dynamic branch predictor with a two-clock-cycle naive Bayes classifier for pipelined RISC microprocessors," Nonlinear Theory and Its Applications, vol. E8-N, no. 3, pp. 235-245 (2017).
Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "A high performance and energy efficient microprocessor with a novel restricted dynamically reconfigurable accelerator," Circuits and Systems, vol. 8, no. 5, pp. 134-147 (2017).
菊谷 雄真, 山野 龍佑, 高前田 伸也, 梅本 敏孝, 小幡 卓司, 早川 潔, "Consideration on Utilization of FPGA Accelerator in CPU/FPGA Mixed Device," 一般社団法人数理科学会論文集, vol. 18, no. 1, pp. 9-14 (2017).
Yuttakonkit Y., Takamaeda-Yamazaki S., and Nakashima Y., "Performance optimization of light-field applications on GPU," IEICE Transactions on Information and Systems, vol. E100-D, (2017), in press.
Shiba K., Omori T., Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Motomura M., Hamada M., and Kuroda T., "A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Online, Seville, Spain (Oct. 10-21, 2020).
Yamamoto K., Ando K., Mertig N., Takemoto T., Yamaoka M., Teramoto H., Sakai A., Takamaeda-Yamazaki S., and Motomura M., "STATICA: A 512-spin 0.25M-weight full-digital annealing processor with a near-memory all-spin-updates-at-once architecture for combinatorial optimization with complete spin-spin interactions," 2020 International Solid-State Circuits Conference (ISSCC 2020), San Francisco Marriott Marquis, San Francisco, USA (Feb. 16-20, 2020).
Ambalathankandy P., Ou Y., Kochiyil J., Takamaeda-Yamazaki S., Motomura M., Asai T., and Ikebe M., "Radiography contrast enhancement: smoothed LHE filter, a practical solution for digital X-rays with Mach band," 2019 International Conference on Digital Image Computing: Techniques and Applications, University of Western Australia, Perth, Australia (Dec. 2-4, 2019).
Kaneko T., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Ternarized backpropagation: a hardware-oriented optimization algorithm for edge-oriented AI devices," The 7th RIEC International Symposium on Brain Functions and Brain Computer, Research Institute of Electrical Communication, Tohoku University, Sendai, Japan (Feb. 22-23, 2019).
Rim S., Suzuki S., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "Approach to reservoir computing with Schmitt trigger oscillator-based analog neural circuits," The 7th Japan-Korea Joint Workshop on Complex Communication Sciences, C5, Alpensia, Pyengonchang, Korea (Jan. 6-9, 2019).
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Dither NN: an accurate neural network with dithering for low bit-precision hardware," The 2018 International Conference on Field-Programmable Technology (FPT'18), Tenbusu-Naha Hall, Naha, Japan (Dec. 10-14, 2018).
Ambalathankandy P., Shimada T., Takamaeda-Yamazaki S., Motomura M., Asai T., and Ikebe M., "Analysis of smoothed LHE methods for processing images with optical illusions," IEEE International Conference on Visual Communications and Image Processing, Tempus Hotel Taichung , Taichung, Taiwan (Dec. 9-12, 2018).
Kudo T., Ueyoshi K., Ando K., Hirose K., Uematsu R., Oba Y., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "Area and energy optimization for bit-serial log-quantized DNN Accelerator with shared accumulators," IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, Vietnam National University, Hanoi, Vietnam (Sep. 12-14, 2018).
Shimada T., Ikebe M., Ambalathankandy P., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Sparse disparity estimation using global phase only correlation for stereo matching acceleration," 2018 IEEE International Conference on Acoustics, Speech and Signal Processing, Calgary Telus Convention Center, Alberta, Canada (Apr. 15-20, 2018).
Iwamaru N., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "A novel iris-center detection algorithm towards gaze estimation targeting molecular cellular automata," International Workshop on Molecular Architectonics 2018, P-25, Osaka University, Osaka, Japan (Mar. 2-3, 2018).
Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Kadomoto J., Miyata T., Hamada M., Kuroda T., and Motomura M., "QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS," 2018 International Solid-State Circuits Conference (ISSCC 2018), San Francisco Marriott Marquis, San Francisco, US (Feb. 11-15, 2018).
Hida I., Ueyoshi K., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "Sign-invariant unsupervised learning facilitates weighted-sum computation in analog neural-network devices," 2017 International Symposium on Nonlinear Theory and Its Applications, Cancun International Convention Center, Cancun, Mexico (Dec. 4-7, 2017).
Hirose K., Uematsu R., Ando K., Orimo K., Ueyoshi K., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Logarithmic Compression for Memory Footprint Reduction in Neural Network Training," 5th International Workshop on Computer Systems and Architectures (CSA 2017), Aomori Prefecture Tourist Center, Aomori, Japan (Nov. 19-22, 2017).
Tanibata A., Schmid A., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects (demo night)," The 27th International Conference on Field-Programmable Logic and Applications, Culture and Convention Center Het Pand, Ghent, Belgium (Sep. 4-8, 2017).
Ando K., Ueyoshi K., Hirose K., Orimo K., Yonekawa H., Sato S., Nakahara H., Ikebe M., Takamaeda-Yamazaki S., Asai T., Kuroda T., and Motomura M., "In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks," 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017), Tufts University, Boston, USA (Aug. 6-9, 2017).
Ando K., Ueyoshi K., Orimo K., Yonekawa H., Sato S., Nakahara H., Ikebe M., Asai T., Takamaeda-Yamazaki S., Kuroda T., and Motomura M., "BRein memory: a 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS," 2017 Symposia on VLSI Technology and Circuits, Rihga Royal Hotel, Kyoto, Japan (Jun. 5-8, 2017).
Yamamoto K., Takamaeda-Yamazaki S., Ikebe M., Asai T., and Motomura M., "A scalable ising model implementation on an FPGA," COOL Chips 20, Yokohama Media & Communications Center, Yokohama, Japan (Apr. 19-21, 2017).
Ando K., Ueyoshi K., Orimo K., Ikebe M., Takamaeda-Yamazaki S., Asai T., and Motomura M., "Throughput analysis of a data-flow reconfigurable array architecture for convolutional neural networks," The 5th RIEC International Symposium on Brain Functions and Brain Computer, Tohoku University, Sendai, Japan (Feb. 27-28, 2017).
Vu H.G., Kajkamhaeng S., Takamaeda-Yamazaki S., and Nakashima Y., "CPRtree: A tree-based checkpointing architecture for heterogeneous FPGA computing," The 4th International Symposium on Computing and Networking (CANDAR 2016), Higashi Hiroshima Arts and Culture Hall, Hiroshima, Japan (Nov. 22-25, 2016).
Kato H., Shimaya S., Fujimoto K., Kameda T., Tran H.T., Takamaeda-Yamazaki S., and Nakashima Y., "CPU Meets VR: A scalable 3D representation of manycores for behavior analysis," 4th International Workshop on Computer Systems and Architectures (CSA 2016), Higashi Hiroshima Arts and Culture Hall, Hiroshima, Japan (Nov. 22-25, 2016).
Rim S., Suzuki S., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "Approach to reservoir computing with Schmitt trigger oscillator-based analog neural circuits," JKCCS 2019 - Best Paper Award, Jan. 8, 2019.
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda S., and Motomura M., "Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware," FPT'18 - Best Paper Award, Dec. 13, 2018.
Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Kadomoto J., Miyata T., Hamada M., Kuroda T., and Motomura M., "QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS," ISSCC 2018 Silkroad Award, Feb. 11, 2018.