Design, Simulation and Evaluation of Basic Analog and Digital CMOS Circuits
Teo Wai Loon Adrian
2001 年度 卒 ／学士（工学）
卒業研究の概要
Signals contain information about the physical world, sometimes directly and sometimes indirectly. For example, let us imagine listening to a radio program of a weather report. The radio generates an acoustic signal that is transmitted to us and processed by our brains. The information that we can obtain directly is 1) there is a speaker nearby 2) the volume of the speaker. The information that we obtain indirectly comes from the contents of the broadcast, the expected temperature and humidity range.
Light signals (which are actually just electro-magnectic wave signals of certain frequencies) enable us to make sense of our surroundings and also to read information from print. Heat signals give us an idea of what to wear or if the house is on fire. Signals form the input to be processed to give us information (output).In other words, someone or something must process all these input signals before we can get any useful information from it. Usually, it is more convenient to have and electronic device perform this processing. Take for example a fire sprinkler system. We could employ a person to switch the system on once he spots a fire in the building. However, it is much more convenient to have an electrical system to monitor the temperature, smoke levels and automatically turn on the sprinklers once these signals exceed a certain level. To enable electronic devices to process these signals, we must first convert them into electrical signals. The conversion process of the signal is beyond the scope of this report. Rather, it will just be assumed that these signals already exist in the electrical domain.
Signals can be divided further into two forms: analog and digital signals. Analog signals are so called because the value of the signal is analogous to the physical signal it represents. And just as the physical signal exhibits a continuous variation over its range of activity, analog signals can take on any value. The electrical circuits that are used to process these signals are called analog circuits. Digital signals on the other hand, take on only a range of quantized (or discretized) values. This signal would be represented by a series of numbers with non-infinite accuracy. The choice of number system to represent the signal greatly affects the complexity of the device used for processing it. For electrical devices, we use the binary number system as we can easily relate the low voltage state (OFF) to 0 and the high voltage state (ON) to 1. We use digital circuits to process these signals.
In this project, I will attempt to design, simulate, and evaluate basic digital and analog CMOS circuits. There are many different digital and analog circuits to choose from, and I believe the best circuits to attempt are those that are elementary enough for entry level designing, and yet instructive and representative of its family of circuits. Adders are one of the building blocks of digital arithmetic and logic units (ALU). Addition forms the basis of many processing functions, from counting to multiplication. Adder circuits that add two binary numbers are thus essential to building digital systems. Amplifiers perform some of the most fundamental tasks of analog computing, namely amplifying weak signals too small to be processed reliably. Operational amplifiers are the standard circuits used for this. Furthermore, by modifying the basic structure of the operational amplifier, we can obtain other circuits like the voltage follower, weighted summer or use it as integrator/differentiator. For these reasons, I have chose to design circuits based on adders and operational amplifiers.
学術論文
Yamazaki H., Akeno I., Nobori K., Asai T., and Ando K., "Proposal and evaluation of recurrent neural network training by multi-phase qua ntization optimizer," Nonlinear Theory and Its Applications, vol. E16-N, no. 1, (2025), in press.
Akeno I., Yamazaki H., Asai T., and Ando K., "Multi-phase-quantization optimizer and its architecture for edge AI training," Nonlinear Theory and Its Applications, vol. E16-N, no. 1, (2025), in press.
Arai F., Hori A., Marukame T., Asai T., and Ando K., "Common Bases Hypothesis: exploring multi-task collaborative learning of neural networks," Nonlinear Theory and Its Applications, vol. , (2025), in press.
Nobori K., Yamazaki H., Marukame T., Asai T., and Ando K., "Evaluation of the encoder-decoder model's common representation acquisition t oward its application in edge computing," Nonlinear Theory and Its Applications, vol. , (2025), in press.
Tamada K., Abe Y., and Asai T., "Resource-efficient streaming architecture for ensemble Kalman filters designed for online learning in physical reservoir computing," Nonlinear Theory and Its Applications, vol. , (2025), in press.
Minagawa K., Ando K., and Asai T., "Performance evaluation of Bayesian neural networks in detecting out-of-distribution image data and a study on data preprocessing," Nonlinear Theory and Its Applications, vol. E15-N, no. 4, pp. 709-724 (2024).
Kojima S., Minagawa K., Saito T., Ando K., and Asai T., "Acquisition of physical kinetics of permanent magnet DC motor by reservoir computing," Nonlinear Theory and Its Applications, vol. E15-N, no. 4, pp. 899-909 (2024).
Tatsumi S., Abe Y., Nishida K., and Asai T., "Physical reservoir replication using small-scale digital calibration reservoir," Nonlinear Theory and Its Applications, vol. E15-N, no. 4, pp. 851-860 (2024).
Saito T., Ando K., and Asai T., "Extending binary neural networks to Bayesian neural networks with probabilistic interpretation of binary weights," IEICE Transactions on Information and Systems, vol. E107-D, no. 8, pp. 949-957 (2024).
（解説記事）浅井 哲也, "Stochastic in-memory computing and its applications to artificial intelligence," IEICE Fundamentals Review, vol. 18, no. 1, pp. 71-78 (2024).
Abe Y., Nakada K., Hagiwara N., Suzuki E., Suda K., Mochizuki S., Terasaki Y., Sasaki T., and Asai T., "Highly-integrable analogue reservoir circuits based on a simple cycle architecture," Scientific Reports, vol. 14, no. 1, 10966 (2024).
Muramatsu S., Nishida K., Ando K., and Asai T., " Stochastic memory device based on a bistable system model with a simple analog circuit," Nonlinear Theory and Its Applications, vol. E15-N, no. 2, pp. 249-261 (2024).
Abe Y., Nishida K., Akai-Kasaya M., and Asai T., "High-order polynomial activation function and regenerative internal weights for FPGA implementation of reservoir computing," Nonlinear Theory and Its Applications, vol. E15-N, no. 2, pp. 262-272 (2024).
(invited paper) Akai-Kasaya M., Igarashi K., and Asai T., "Cellar automata models for reservoir computing in single-walled carbon nanotube network complexed with polyoxometalate," Nonlinear Theory and Its Applications, vol. E15-N, no. 1, pp. 17-35 (2024).
Hagiwara N., Kunimi T., Ando K., Akai-Kasaya M., and Asai T., "Design and evaluation of brain-inspired predictive coding networks based on the free-energy principle for novel neuromorphic hardware," Nonlinear Theory and Its Applications, vol. E15-N, no. 1, pp. 107-118 (2024).
Kaneko T., Momose H., Suwa H., Ono T., Hayata Y., Kouno K., and Asai T., "On the control of computing-in-memory devices with resource-efficient digital circuits towards their on-chip learning," Nonlinear Theory and Its Applications, vol. E14-N, no. 4, pp. 639-651 (2023).
Yamakawa S., Ando K., Akai-Kasaya M., and Asai T., "A novel small-signal detection method using divergence properties of second-order linear differential equations," Electronics Letters, vol. 59, no. 16, e12928 (2023).
Hagiwara N., Asai T., Ando K., and Akai-Kasaya M., "Fabrication and training of 3D conductive polymer networks for neuromorphic wetware," Advanced Functional Materials, vol. 33, no. 42, 02300903 (2023).
Wen Q., Shiramatsu T.I., Takahashi H., and Asai T., "Active charge balancer for CMOS integration of an array of neural stimulators," Nonlinear Theory and Its Applications, vol. E14-N, no. 2, pp. 319-333 (2023).
Yamagishi Y., Kaneko T., Akai-Kasaya M., and Asai T., "Holmes: A hardware-oriented optimizer using logarithms," IEICE Transactions on Information and Systems, vol. E105-D, no. 12, pp. 2040-2047 (2022).
Yoshida K., Akai-Kasaya M., and Asai T., "A 1-Msps 500-node FORCE learning accelerator for reservoir computing," Journal of Signal Processing, vol. 26, no. 4, pp. 103-106 (2022).
Ou Y., Ambalathankandy P., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Real-time tone mapping: a survey and cross-implementation hardware benchmark," IEEE Transactions on Circuits and Systems for Video Technology, vol. 32, no. 5, pp. 2666-2686 (2022).
Amemiya Y., Ali E.J., Hagiwara N., Akai-Kasaya M., and Asai T., "Heuristic model for configurable polymer wire synaptic devices," Nonlinear Theory and Its Applications, vol. E13-N, no. 2, pp. 379-384 (2022).
Kubota H., Hasegawa T., Akai-Kasaya M., and Asai T., "Noise sensitivity of physical reservoir computing in a ring array of atomic switches," Nonlinear Theory and Its Applications, vol. E13-N, no. 2, pp. 373-378 (2022).
Sasaki Y., Muramatsu S., Nishida K., Akai-Kasaya M., and Asai T., "Digital implementation of a multilayer perceptron based on stochastic computing with online learning function," Nonlinear Theory and Its Applications, vol. E13-N, no. 2, pp. 324-329 (2022).
Ali E.J., Amemiya Y., Akai-Kasaya M., and Asai T., "Smart hardware architecture with random weight elimination and weight balancing algorithms," Nonlinear Theory and Its Applications, vol. E13-N, no. 2, pp. 336-342 (2022).
Nakada K., Suzuki S., Suzuki E., Terasaki Y., Asai T., and Sasaki T., "An information theoretic parameter tuning for MEMS-based reservoir computing," Nonlinear Theory and Its Applications, vol. E13-N, no. 2, pp. 459-464 (2022).
Kan S., Asai T., Nakajima K., and Akai-Kasaya M., "Physical implementation of reservoir computing through electrochemical reaction," Advanced Science, vol. 9, no. 6, 2104076 (2022).
（解説記事）浅井 哲也, "Re-pioneering stochastic computing towards low-power edge-AI devices with inference and online learning abilities," 情報処理, vol. 63, no. 3, pp. e8-e14 (2022).
Kubota H., Hasegawa T., Akai-Kasaya M., and Asai T., "Behavioral model of molecular gap-type atomic switches and its SPICE integration," Circuits and Systems, vol. 13, no. 1, pp. 1-12 (2022).
Akai-Kasaya M., Takeshima Y., Kan S., Nakajima K., Oya T., and Asai T., "Performance of reservoir computing in a random network of single-walled carbon nanotubes complexed with polyoxometalate," Neuromorphic Computing and Engineering, vol. 2, no. 1, 014003 (2022).
Kan S., Sasaki Y., Asai T., and Akai-Kasaya M., "Applying a molecular device to stochastic computing operation for a hardware AI system design," Journal of Signal Processing, vol. 25, no. 6, pp. 221-225 (2021).
Yamagishi Y., Kaneko T., Akai-Kasaya M., and Asai T., "Hardware-oriented deep reinforcement learning for edge computing," Nonlinear Theory and Its Applications, vol. E12-N, no. 3, pp. 526-544 (2021).
Kubota H., Hasegawa T., Akai-Kasaya M., and Asai T., "Reservoir computing on atomic switch arrays with high precision and excellent memory characteristics," Journal of Signal Processing, vol. 25, no. 4, pp. 123-126 (2021).
Krukowski P., Chaunchaiyakul S., Akai-Kasaya M., Saito A., Osuga H., and Kuwahara Y., "Adsorption and Light Emission of a Racemic Mixture of [7]thiaheterohelicene-2,13-carboxaldehyde on Au(111), Cu(001), and NiAl(110) Surfaces Investigated Using a Scanning Tunneling Microscope," The Journal of Physical Chemistry C, vol. 125, no. 17, pp. 9419-9427 (2021).
Kan S., Nakajima K., Takeshima Y., Asai T., Kuwahara Y., and Akai-Kasaya M., "Simple reservoir computing capitalizing on the nonlinear response of materials: Theory and physical implementations," Physical Review Applied, vol. 15, no. 2, 024030 (2021).
Hagiwara N., Sekizaki S., Kuwahara Y., Asai T., and Akai-Kasaya M., "Long- and short-term conductance control of artificial polymer wire synapses," Polymers, vol. 13, no. 2, 312 (2021).
Hirayama Y., Asai T., Motomura M., and Takamaeda-Yamazaki S., "A hardware-efficient weight sampling circuit for Bayesian neural networks," International Journal of Networking and Computing, vol. 10, no. 2, pp. 84-93 (2020).
Akai-Kasaya M., Hagiwara N., Hikita W., Okada M., Sugito Y., Kuwahara Y., and Asai T., "Evolving conductive polymer neural networks on wetware," Japanese Journal of Applied Physics, vol. 59, no. 5, 060601 (2020).
Momose H., Kaneko T., and Asai T., "Systems and circuits for AI chips and their trends," Japanese Journal of Applied Physics, vol. 59, no. 5, 050502 (2020).
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Dither NN: hardware/algorithm co-design for accurate quantized neural networks," IEICE Transactions on Information and Systems, vol. E102, pp. 2341-2353 (2019).
Yamamoto K., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "FPGA-based annealing processor with time-division multiplexing," IEICE Transactions on Information and Systems, vol. E102-D, no. 12, pp. 2295-2305 (2019).
Kaneko T., Orimo K., Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "A study on a low power optimization algorithm for an edge-AI Device," Nonlinear Theory and Its Applications, vol. E10-N, no. 4, pp. 373-389 (2019).
Kaneko T., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Hardware-oriented algorithm and architecture for generative adversarial networks," Journal of Signal Processing, vol. 23, no. 4, pp. 151-154 (2019).
Sasaki K., Okamoto S., Tashiro S., Asai T., and Kasai S., "Formation and characterization of charge coupled structure of polyoxometalate particles and a GaAs-based nanowire for readout of molecular charge states," Japanese Journal of Applied Physics, vol. 58, no. SD, SDDE13 (2019).
（研究紹介）百瀬 啓, 肥田 格, 浅井 哲也, "学習も推論も！人工知能スタータキット AI Arduino ーマイコンには荷が重すぎるニューラル・ネットワーク計算をFPGAで強力アシストー," トランジスタ技術, vol. 2018, no. 11, pp. 100-101 (2018).
Hirose K., Uematsu R., Ando K., Ueyoshi K., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "Quantization error-based regularization for hardware-aware neural network training," Nonlinear Theory and Its Applications, vol. E9-N, no. 4, pp. 453-465 (2018).
Achararit P., Hida I., Marukame T., Asai T., and Hara-Azumi Y., "Structural exploration of stochastic neural networks for severely-constrained 3D memristive devices," Nonlinear Theory and Its Applications, vol. E9-N, no. 4, pp. 466-478 (2018).
Ambalathankandy P., Takamaeda-Yamazaki S., Motomura M., Asai T., Ikebe M., and Kusano H., "Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA," Microprocessors and Microsystems, vol. 61, pp. 21-31 (2018).
Tanaka H., Akai-Kasaya M., Termeh A.Y., Hong L., Fu L., Tamukoh H., Tanaka D., Asai T., and Ogawa T., "A molecular neuromorphic network device consisting of single-walled carbon nanotubes complexed with polyoxometalate," Nature Communications, vol. 9, no. 1, 2693 (2018).
Ando K., Ueyoshi K., Orimo K., Yonekawa H., Sato S., Nakahara H., Takamaeda-Yamazaki S., Ikebe M., Asai T., Kuroda T., and Motomura M., "BRein memory: a single-chip binary/ternary reconfigurable in-memory deep neural network accelerator achieving 1.4TOPS at 0.6W," IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 983-994 (2018).
Tanibata A., Schmid A., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "Proto-computing architecture over a digital medium aiming at real-time video processing," Complexity, vol. 2018, 3618621 (2018).
（解説記事）百瀬 啓, 浅井 哲也, "Deep learning chips and AI computing," 人工知能学会誌, vol. 33, no. 1, pp. 23-30 (2018).
Tsuji T., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "6-DoF camera position and posture estimation based on local patches of image sequence," Journal of Signal Processing, vol. 21, no. 4, pp. 191-194 (2017).
Ando K., Takamaeda-Yamazaki S., Ikebe M., Asai T., and Motomura M., "A multithreaded CGRA for convolutional neural network processing," Circuits and Systems, vol. 8, no. 6, pp. 149-170 (2017).
Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "An energy-efficient dynamic branch predictor with a two-clock-cycle naive Bayes classifier for pipelined RISC microprocessors," Nonlinear Theory and Its Applications, vol. E8-N, no. 3, pp. 235-245 (2017).
Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "A high performance and energy efficient microprocessor with a novel restricted dynamically reconfigurable accelerator," Circuits and Systems, vol. 8, no. 5, pp. 134-147 (2017).
Marukame T., Ueyoshi K., Asai T., Motomura M., Schmid A., Suzuki M., Higashi Y., and Mitani Y., "Error tolerance analysis of deep learning hardware using restricted Boltzmann machine towards low-power memory implementation," IEEE Transactions on Circuits and Systems II, vol. 64, no. 4, pp. 462-466 (2017).
Yamamoto K., Ikebe M., Asai T., and Motomura M., "FPGA-based stream processing for frequent itemset mining with incremental multiple hashes," Circuits and Systems, vol. 7, no. 10, pp. 3299-3309 (2016).
Ueyoshi K., Marukame T., Asai T., Motomura M., and Schmid A., "FPGA implementation of a scalable and highly parallel architecture for restricted Boltzmann machines," Circuits and Systems, vol. 7, no. 9, pp. 2132-2141 (2016).
Ueyoshi K., Marukame T., Asai T., Motomura M., and Schmid A., "Robustness of hardware-oriented restricted Boltzmann machines in deep belief networks for reliable processing," Nonlinear Theory and Its Applications, vol. E7-N, no. 3, pp. 395-406 (2016).
Ushida M., Schmid A., Asai T., Ishimura K., and Motomura M., "Motion vector estimation of textureless objects exploiting reaction-diffusion cellular automata," International Journal of Unconventional Computing, vol. 12, no. 2-3, pp. 169-187 (2016).
Ishimura K., Schmid A., Asai T., and Motomura M., "Stochastic resonance induced by internal noise in a unidirectional network of excitable FitzHugh-Nagumo neurons," Nonlinear Theory and Its Applications, vol. 7, no. 2, pp. 164-175 (2016).
Nakada K., Miura K., and Asai T., "Dynamical systems design of silicon neurons using phase reduction method," Nonlinear Theory and Its Applications, vol. 7, no. 2, pp. 95-109 (2016).
Ikebe M., Uchida D., Take Y., Someya M., Chikuda S., Matsuyama K., Asai T., Kuroda T., and Motomura M., "3D stacked imager featuring inductive coupling channels for high speed/low-noise image transfer," ITE Transactions on Media Technology and Applications, vol. 4, no. 2, pp. 142-148 (2016).
El-Sankary K., Asai T., Kuroda T., and Motomura M., "Crosstalk rejection in 3D-stacked inter-chip communication with blind source separation," IEEE Transactions on Circuits and Systems II, vol. 62, no. 8, pp. 726-730 (2015).
Ishimura K., Komuro K., Schmid A., Asai T., and Motomura M., "FPGA implementation of hardware-oriented reaction-diffusion cellular automata models," Nonlinear Theory and Its Applications, vol. 6, no. 2, pp. 252-262 (2015).
Fukuda E.S., Inoue H., Takenaka T., Kim D., Sadahisa T., Asai T., and Motomura M., "Enhancing memcached by caching its data and functionalities at network interface," IPSJ Journal, vol. 56, no. 3, pp. 143-152 (2015).
Kim D., Hida I., Fukuda E.S., Asai T., and Motomura M., "Reducing power and energy consumption of nonvolatile microcontrollers with transparent on-chip instruction cache," Circuits and Systems, vol. 5, no. 11, pp. 253-264 (2014).
Gonzalez-Carabarin L., Asai T., and Motomura M., "Application of nonlinear systems for designing low-power logic gates based on stochastic resonance," Nonlinear Theory and Its Applications, vol. 5, no. 4, pp. 445-455 (2014).
Ishimura K., Komuro K., Schmid A., Asai T., and Motomura M., "Image steganography based on reaction diffusion models toward hardware implementation," Nonlinear Theory and Its Applications, vol. 5, no. 4, pp. 456-465 (2014).
Mori M., Itou T., Ikebe M., Asai T., Kuroda T., and Motomura M., "FPGA-based design for motion-vector estimation exploiting high-speed imaging and its application to motion classification with neural networks," Journal of Signal Processing, vol. 18, no. 4, pp. 165-168 (2014).
Gonzalez-Carabarin L., Asai T., and Motomura M., "Low-power asynchronous digital pipeline based on mismatch-tolerant logic gates," IEICE Electronics Express, vol. 11, no. 15, pp. 20140632/1-9 (2014).
Ishimura K., Asai T., and Motomura M., "Chaotic resonance in forced Chua's oscillators," Journal of Signal Processing, vol. 17, no. 6, pp. 231-238 (2013).
Fukuda E.S., Kawashima H., Inoue H., Asai T., and Motomura M., "C-based design of window join for dynamically reconfigurable hardware," Journal of Computer Science and Engineering, vol. 20, no. 2, pp. 1-9 (2013).
Sanada Y., Ohira T., Chikuda S., Igarashi M., Ikebe M., Asai T., and Motomura M., "FPGA implementation of single-image super resolution based on frame-bufferless box filtering," Journal of Signal Processing, vol. 17, no. 4, pp. 111-114 (2013).
Utagawa A., Asai T., and Amemiya Y., "Noise-induced phase synchronization among analog MOS oscillator circuits," Fluctuation and Noise Letters, vol. 11, no. 2, pp. 1250007/1-11 (2012).
Gong X., Asai T., and Motomura M., "Excitable reaction-diffusion media with memristors," Journal of Signal Processing, vol. 16, no. 4, pp. 283-286 (2012).
Matsuura M., Asai T., and Motomura M., "Noise-induced phase synchronization among simple digital counters," Journal of Signal Processing, vol. 16, no. 4, pp. 279-282 (2012).
Gonzalez-Carabarin L., Asai T., and Motomura M., "Impact of noise on spike transmission through serially-connected electrical FitzHugh-Nagumo circuits with subthreshold and suprathreshold interconductances," Journal of Signal Processing, vol. 16, no. 6, pp. 503-509 (2012).
Narumi T., Suzuki M., Hidaka Y., Asai T., and Kai S., "Active brownian motion in threshold distribution of a Coulomb blockade model," Physical Review E, vol. 84, no. 5, pp. 051137/1-5 (2011).
Utagawa A., Asai T., and Amemiya Y., "Stochastic resonance in simple analog circuits with a single operational amplifier having a double-well potential," Nonlinear Theory and Its Applications, vol. 2, no. 4, pp. 409-416 (2011).
Oya T., Schmid A., Asai T., and Utagawa A., "Stochastic resonance in a balanced pair of single-electron boxes," Fluctuation and Noise Letters, vol. 10, no. 3, pp. 267-275 (2011).
Asai T. and Motoike I.N., "Self-organizing striped and spotted patterns on a discrete reaction-diffusion model," Nonlinear Theory and Its Applications, vol. 2, no. 3, pp. 363-371 (2011).
Utagawa A., Asai T., and Amemiya Y., "High-fidelity pulse density modulation in neuromorphic electric circuits utilizing natural heterogeneity," Nonlinear Theory and Its Applications, vol. 2, no. 2, pp. 218-225 (2011).
Fujita D., Asai T., and Amemiya Y., "A neuromorphic MOS circuit imitating jamming avoidance response of Eigenmannia," Nonlinear Theory and Its Applications, vol. 2, no. 2, pp. 205-217 (2011).
Kikombo A.K., Asai T., and Amemiya Y., "Neuro-morphic circuit architectures employing temporal noises and device fluctuations to improve signal-to-noise ratio in a single-electron pulse-density modulator," International Journal of Unconventional Computing, vol. 7, no. 1-2, pp. 53-64 (2011).
Ueno K., Asai T., and Amemiya Y., "Low-power temperature-to-frequency converter consisting of subthreshold CMOS circuits for integrated smart temperature sensors," Sensors and Actuators A: Physical, vol. 165, no. 1, pp. 132-137 (2011).
Akoh N., Asai T., Yanagida T., Kawai T., and Amemiya Y., "A behavioral model of unipolar resistive RAMs and its application to HSPICE integration," IEICE Electronics Express, vol. 7, no. 19, pp. 1467-1473 (2010).
Ueno K., Hirose T., Asai T., and Amemiya Y., "A 1-uW, 600-ppm/°C current reference circuit consisting of subthreshold CMOS circuits," IEEE Transactions on Circuits and Systems II, vol. 57, no. 9, pp. 681-685 (2010).
Tsugita Y., Ueno K., Hirose T., Asai T., and Amemiya Y., "An on-chip PVT compensation technique with current monitoring circuit for low-voltage CMOS digital LSIs," IEICE Transactions on Electronics, vol. E93-C, no. 6, pp. 835-841 (2010).
Asai S., Ueno K., Asai T., and Amemiya Y., "High-resistance resistor consisting of a subthreshold CMOS differential pair," IEICE Transactions on Electronics, vol. E93-C, no. 6, pp. 741-746 (2010).
Hirai T., Asai T., and Amemiya Y., "CMOS phase-shift oscillator based on the conduction of heat," Journal of Circuits, Systems, and Computers, vol. 19, no. 4, pp. 763-772 (2010).
上野 憲一, 廣瀬 哲也, 浅井 哲也, 雨宮 好仁, "Floating millivolt reference for PTAT current generation in subthreshold MOS LSIs," 映像情報メディア学会誌, vol. 63, no. 12, pp. 1877-1880 (2009).
Ueno K., Hirose T., Asai T., and Amemiya Y., "A 300-nW, 15-ppm/°C, 20-ppm/V CMOS voltage reference circuit consisting of subthreshold MOSFETs," IEEE Journal of Solid-State Circuits, vol. 44, no. 7, pp. 2047-2054 (2009).
Hirose T., Hagiwara A., Asai T., and Amemiya Y., "A highly sensitive thermosensing CMOS circuit based on self-biasing circuit technique," IEEJ Transactions on Electrical and Electronic Engineering, vol. 4, no. 2, pp. 278-286 (2009).
Kikombo A.K., Schmid A., Asai T., Leblebici Y., and Amemiya Y., "A bio-inspired image processor for edge detection with single-electron circuits," Journal of Signal Processing, vol. 13, no. 2, pp. 133-144 (2009).
Kikombo A.K., Asai T., and Amemiya Y., "An elementary neuro-morphic circuit for visual motion detection with single-electron devices based on correlation neural networks," Journal of Computational and Theoretical Nanoscience, vol. 6, no. 1, pp. 89-95 (2009).
Kasai S. and Asai T., "Stochastic resonance in Schottky wrap gate-controlled GaAs nanowire field effect transistors and their networks," Applied Physics Express, vol. 1, no. 8, pp. 083001/1-3 (2008).
Kikombo A.K., Hirose T., Asai T., and Amemiya Y., "Non-linear phenomena in electronic systems consisting of coupled single-electron oscillators," Chaos, Solitons and Fractals, vol. 37, no. 1, pp. 100-107 (2008).
Hirose T., Asai T., and Amemiya Y., "Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs," IEICE Electronics Express, vol. 5, no. 6, pp. 204-210 (2008).
Tovar G.M., Asai T., Hirose T., and Amemiya Y., "Critical temperature sensor based on oscillatory neuron models," Journal of Signal Processing, vol. 12, no. 1, pp. 17-24 (2008).
Tovar G.M., Asai T., Fujita D., and Amemiya Y., "Analog MOS circuits implementing a temporal coding neural model," Journal of Signal Processing, vol. 12, no. 6, pp. 423-432 (2008).
Yamada K., Asai T., Hirose T., and Amemiya Y., "On digital LSI circuits exploiting collision-based fusion gates," International Journal of Unconventional Computing, vol. 4, no. 1, pp. 45-59 (2008).
Nakada K., Asai T., Hirose T., Hayashi H., and Amemiya Y., "A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters," Neurocomputing, vol. 71, no. 1-3, pp. 3-12 (2007).
Hirose T., Asai T., and Amemiya Y., "Pulsed neural networks consisting of single-flux-quantum spiking neurons," Physica C, vol. 463-465, no. 1, pp. 1072-1075 (2007).
Kikombo A.K., Oya T., Asai T., and Amemiya Y., "Discrete dynamical systems consisting of single-electron circuits," International Journal of Bifurcation and Chaos, vol. 17, no. 10, pp. 3613-3617 (2007).
Oya T., Motoike I.N., and Asai T., "Single-electron circuits performing dendritic pattern formation with nature-inspired cellular automata," International Journal of Bifurcation and Chaos, vol. 17, no. 10, pp. 3651-3655 (2007).
Fukuda E.S., Tovar G.M., Asai T., Hirose T., and Amemiya Y., "Neuromorphic CMOS circuits implementing a novel neural segmentation model based on symmetric STDP learning," Journal of Signal Processing, vol. 11, no. 6, pp. 439-444 (2007).
Takahashi M., Asai T., Hirose T., and Amemiya Y., "A CMOS reaction-diffusion device using minority-carrier diffusion in semiconductors," International Journal of Bifurcation and Chaos, vol. 17, no. 5, pp. 1713-1719 (2007).
Oya T., Asai T., and Amemiya Y., "Stochastic resonance in an ensemble of single-electron neuromorphic devices and its application to competitive neural networks," Chaos, Solitons and Fractals, vol. 32, no. 2, pp. 855-861 (2007).
Ueno K., Hirose T., Asai T., and Amemiya Y., "CMOS smart sensor for monitoring the quality of perishables," IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 798-803 (2007).
Oya T., Asai T., and Amemiya Y., "A single-electron reaction-diffusion device for computation of a Voronoi diagram," International Journal of Unconventional Computing, vol. 3, no. 4, pp. 271-284 (2007).
Suzuki Y., Takayama T., Motoike I.N., and Asai T., "Striped and spotted pattern generation on reaction-diffusion cellular automata -- theory and LSI implementation --," International Journal of Unconventional Computing, vol. 3, no. 1, pp. 1-13 (2007).
Nakada K., Asai T., and Hayashi H., "Analog VLSI implementation of resonate-and-fire neuron," International Journal of Neural Systems, vol. 16, no. 6, pp. 445-456 (2006).
Hirose T., Asai T., and Amemiya Y., "Power-supply circuits for ultralow-power subthreshold MOS-LSIs," IEICE Electronics Express, vol. 3, no. 22, pp. 464-468 (2006).
Hirose T., Asai T., and Amemiya Y., "Spiking neuron devices consisting of single-flux-quantum circuits," Physica C, vol. 445-448, no. N/A, pp. 1020-1023 (2006).
Tovar G.M., Hirose T., Asai T., and Amemiya Y., "Neuromorphic MOS circuits exhibiting precisely-timed synchronization with silicon spiking neurons and depressing synapses," Journal of Signal Processing, vol. 10, no. 6, pp. 391-397 (2006).
Yamada K., Motoike I.N., Asai T., and Amemiya Y., "Design methodologies for compact logic circuits based on collision-based computing," IEICE Electronics Express, vol. 3, no. 13, pp. 292-298 (2006).
Oya T., Asai T., Kagaya R., Hirose T., and Amemiya Y., "Neuronal synchrony detection on single-electron neural networks," Chaos, Solitons and Fractals, vol. 27, no. 4, pp. 887-894 (2006).
Asai T., Kamiya T., Hirose T., and Amemiya Y., "A subthreshold analog MOS circuit for Lotka-Volterra chaotic oscillator," International Journal of Bifurcation and Chaos, vol. 16, no. 1, pp. 207-212 (2006).
鈴木 洋平, 高山 貴裕, 元池 N. 育子, 浅井 哲也, "縞・斑点画像パターンの修復を行う反応拡散モデルとそのLSI化," 電子情報通信学会論文誌A, vol. J87-A, no. 11, pp. 1272-1281 (2005).
Asai T., De Lacy Costello B., and Adamatzky A., "Silicon implementation of a chemical reaction-diffusion processor for computation of Voronoi diagram," International Journal of Bifurcation and Chaos, vol. 15, no. 10, pp. 3307-3320 (2005).
Ikebe M. and Asai T., "A digital vision chip for early feature extraction with rotated template-matching cellular automata," Journal of Robotics and Mechatronics, vol. 17, no. 4, pp. 372-377 (2005).
Hirose T., Matsuoka T., Taniguchi K., Asai T., and Amemiya Y., "Ultralow-power current reference circuit with low temperature dependence," IEICE Transactions on Electronics, vol. E88-C, no. 6, pp. 1142-1147 (2005).
Nakada K., Asai T., and Amemiya Y., "Analog CMOS implementation of a CNN-based locomotion controller with floating-gate devices," IEEE Transactions on Circuits and Systems I, vol. 52, no. 6, pp. 1095-1103 (2005).
Oya T., Schmid A., Asai T., Leblebici Y., and Amemiya Y., "On the fault tolerance of a clustered single-electron neural network for differential enhancement," IEICE Electronics Express, vol. 2, no. 3, pp. 76-80 (2005).
Oya T., Asai T., Fukui T., and Amemiya Y., "Reaction-diffusion systems consisting of single-electron oscillators," International Journal of Unconventional Computing, vol. 1, no. 2, pp. 177-194 (2005).
Asai T., Kanazawa Y., Hirose T., and Amemiya Y., "Analog reaction-diffusion chip imitating the Belousov-Zhabotinsky reaction with hardware Oregonator model," International Journal of Unconventional Computing, vol. 1, no. 2, pp. 123-147 (2005).
Nakada K., Asai T., and Amemiya Y., "Biologically-inspired locomotion controller for a quadruped walking robot: Analog IC implementation of a CPG-based controller," Journal of Robotics and Mechatronics, vol. 16, no. 4, pp. 397-403 (2004).
Matsubara H., Asai T., Hirose T., and Amemiya Y., "Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata," IEICE Electronics Express, vol. 1, no. 9, pp. 248-252 (2004).
Kanazawa Y., Asai T., Hirose T., and Amemiya Y., "A MOS circuit for bursting neural oscillators with excitable Oregonators," IEICE Electronics Express, vol. 1, no. 4, pp. 73-76 (2004).
Kagaya R., Ikebe M., Asai T., and Amemiya Y., "On-chip fixed-pattern-noise canceling with non-destructive intermediate readout circuitry for CMOS active-pixel sensors," WSEAS Transactions on Circuits and Systems, vol. 3, no. 3, pp. 477-479 (2004).
Asai T., Adamatzky A., and Amemiya Y., "Towards reaction-diffusion computing devices based on minority-carrier transport in semiconductors," Chaos, Solitons and Fractals, vol. 20, no. 4, pp. 863-876 (2004).
Nakada K., Asai T., and Amemiya Y., "Design of an artificial central pattern generator with feedback controller," Intelligent Automation and Soft Computing, vol. 10, no. 2, pp. 185-192 (2004).
Kanazawa Y., Asai T., Ikebe M., and Amemiya Y., "A novel CMOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection," International Journal of Robotics and Automation, vol. 19, no. 4, pp. 206-212 (2004).
Oya T., Takahashi Y., Ikebe M., Asai T., and Amemiya Y., "A single-electron circuit as a discrete dynamical system," Superlattices and Microstructures, vol. 34, no. 3-6, pp. 253-258 (2003).
Nakada K., Asai T., and Amemiya Y., "An analog central pattern generator for interlimb coordination in quadruped locomotion," IEEE Transactions on Neural Networks, vol. 14, no. 5, pp. 1356-1365 (2003).
Asai T., Kanazawa Y., and Amemiya Y., "A subthreshold MOS neuron circuit based on the Volterra system," IEEE Transactions on Neural Networks, vol. 14, no. 5, pp. 1308-1312 (2003).
Kanazawa Y., Asai T., and Amemiya Y., "Basic circuit design of a neural processor: analog CMOS implementation of spiking neurons and dynamic synapses," Journal of Robotics and Mechatronics, vol. 15, no. 2, pp. 208-218 (2003).
Oya T., Asai T., and Amemiya Y., "Single electron logic device with simple structure," 重複_Electronics Letters, vol. 39, no. 13, pp. 965-967 (2003).
Oya T., Asai T., Fukui T., and Amemiya Y., "A majority-logic device using an irreversible single-electron box," IEEE Transactions on Nanotechnology, vol. 2, no. 1, pp. 15-22 (2003).
Oya T., Asai T., Fukui T., and Amemiya Y., "A majority-logic nanodevice using a balanced pair of single-electron boxes," Journal of Nanoscience and Nanotechnology, vol. 2, no. 3/4, pp. 333-342 (2002).
Inokuchi T., Yamada T., Asai T., and Amemiya Y., "Analog computation using quantum-flux parametron devices," Physica C, vol. 357-360, no. 2, pp. 1618-1621 (2001).
Asai T., Sunayama T., Amemiya Y., and Ikebe M., "A MOS vision chip based on the cellular-automaton processing," Japanese Journal of Applied Physics, vol. 40, no. 4B, pp. 2585-2592 (2001).
Yamada T., Akazawa M., Asai T., and Amemiya Y., "Boltzmann-machine neural network devices using single-electron tunnelling," Nanotechnology, vol. 12, no. 1, pp. 60-67 (2001).
Sunayama T., Ikebe M., Asai T., and Amemiya Y., "Cellular νMOS circuits performing edge detection with difference-of-Gaussian Filters," Japanese Journal of Applied Physics, vol. 39, no. 4B, pp. 2278-2286 (2000).
書籍／チャプター
Akai-Kasaya M. and Asai T., "Evolving Conductive Polymer Neural Networks on Wetware," Handbook of Unconventional Computing, Adamatzky A. Ed., vol. 2, World Scientific (2021).
Asai T. and Peper F., "Explorations in Morphic Architectures," Emerging Nanoelectronic Devices, Chen A., Hutchby J., ZhirnovV, and Bourianoff G., Eds, Wiley, New Jersey (2015).
Asai T., "Memristor-CMOS-hybrid synaptic devices exhibiting spike-timing-dependent plasticity," VLSI: Circuits for Emerging Applications, Wojcicki T. and Iniewski I., Eds., CRC Press (2014).
Asai T., "Reaction-diffusion media with excitable Oregonators coupled by memristors," Memristor Networks, Adamatzky A. and Chua L., eds., Springer (2013).
Kikombo A.K., Asai T., and Amemiya Y., "Exploiting temporal noises and device fluctuations in enhancing fidelity of pulse-density modulator consisting of single-electron neural circuits," Neural Information Processing, Leung C.-S., Lee M., and Chan J.H., Eds., Lecture Notes in Computer Science, vol. 5864, pp. 384-391, Springer Berlin / Heidelberg (2009).
Tovar G.M., Asai T., and Amemiya Y., "Noise-tolerant analog circuits for sensory segmentation based on symmetric STDP learning," Advances in Neuro-Information Processing, Koppen M., Kasabov N., and Coghill G, Eds., Lecture Notes in Computer Science, vol. 5507, pp. 851-858, Springer, Berlin / Heidelberg (2009).
Asai T. and Oya T., "Nature-inspired single-electron circuits," Artificial Life Models in Hardware, Adamatzky A. and Komosinski M., Eds., pp. 133-160, Springer (2009).
Tovar G.M., Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "Analog CMOS circuits implementing neural segmentation model based on symmetric STDP learning," Neural Information Processing, Ishikawa M., Doya K., Miyamoto H., and Yamakawa T., Eds., Lecture Notes in Computer Science, vol. 4985, pp. 117-126, Springer, Berlin / Heidelberg (2008).
Utagawa A., Asai T., Hirose T., and Amemiya Y., "Noise shaping pulse-density modulation in inhibitory neural networks with subthreshold neuron circuits," Brain-Inspired IT III, Natsume K., Hanazawa A., and Miki T., Eds, International Congress Series, vol. 1301, pp. 71-74, Elsevier, Netherlands (2007).
Nakada K., Asai T., and Hayashi H., "Synchronization properties of pulse-coupled resonate-and-fire neuron circuits and their application," Brain-Inspired IT III, Natsume K., Hanazawa A., and Miki T., Eds, International Congress Series, vol. 1301, pp. 148-151, Elsevier, Netherlands (2007).
浅井 哲也, 元池 N. 育子, "自己組織化フラクタル材料---樹状パターンを生成する量子ドット回路," 自己組織化ナノマテリアル---フロントランナー60人に聞くナノテクノロジーの新潮流, 山口 智彦, 下村 正嗣 編, Chapter 6.2, pp. 302-306, フロンティア出版, 東京 (2007).（分担執筆）
Nakada K., Asai T., and Hayashi H., "Burst synchronization in two pulse-coupled resonate-and-fire neuron circuits," Professional Practice in Artificial Intelligence, IFIP International Federation for Infornation Processing, Debenham J., Ed., vol. 218, pp. 285-294, Springer, Boston (2006).
Yamada K., Asai T., Motoike I.N., and Amemiya Y., "On digital VLSI circuits exploiting collision-based fusion gates," From Utopian to Genuine Unconventional Computers, Teuscher C. and Adamatzky A., Eds., pp. 1-16, Luniver Press, U.K. (2006).
Hirose T., Ueno K., Asai T., and Amemiya Y., "Single-flux-quantum circuits for spiking neuron devices," Brain-Inspired IT II, Ishii K., Natsume K., and Hanazawa A., Eds., International Congress Series, vol. 1291, pp. 221-224, Elsevier, Netherlands (2006).
Oya T., Asai T., Kagaya R., Kasai S., and Amemiya Y., "Stochastic resonance among single-electron neurons on Schottky wrap-gate devices," Brain-Inspired IT II, Ishii K., Natsume K., and Hanazawa A., Eds., International Congress Series, vol. 1291, pp. 213-216, Elsevier, Netherlands (2006).
Oya T., Asai T., and Amemiya Y., "A single-electron reaction-diffusion device for computation of a Voronoi diagram," Unconventional Computing 2005: From Cellular Automata to Wetware, Teuscher C. and Adamatzky A., Eds., pp. 13-26, Luniver Press, U.K. (2005).
Suzuki Y., Takayama T., Motoike I.N., and Asai T., "Striped and spotted pattern generation on reaction-diffusion cellular automata -- theory and LSI implementation --," Unconventional Computing 2005: From Cellular Automata to Wetware, Teuscher C. and Adamatzky A., Eds., pp. 41-54, Luniver Press, U.K. (2005).
Asai T., "A neuromorphic CMOS family and its application," Brain-Inspired IT I, Nakagawa H., Ishii K., and Miyamoto H., Eds., International Congress Series, vol. 1269, pp. 173-176, Elsevier, Netherlands (2004).
Asai T., "Unconventional AI and neuromorphic computing driven by emerging devices and materials," 2018 IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, USA (Jun. 17-18, 2018).
秋永 広幸, 島 久, 内藤 泰久, 浅井 哲也, "アナログ型抵抗変化ニューロデバイス・システムのソフト・ハード一体型研究開発," 電子情報通信学会集積回路研究会, Kikai Shinko Kaikan, Tokyo, Japan (Apr. 19-20, 2018).
Ikebe M., Uchida D., Take Y., Asai T., Kuroda T., and Motomura M., "3D stacked image sensor featuring low noise inductive coupling channels," The 3rd International Workshop on Image Sensors and Imaging Systems, pp. 15-16, Tokyo Institute of Technology, Tokyo, Japan (Nov. 17-18, 2016).
浅井 哲也, "学習型ハードウェアとその応用・発展の展望," 第9回情報ネットワーク科学研究会, Tokyo Metropolitan University, Tokyo, Japan (May 27, 2016).
赤井 恵, 浅井 哲也, "シナプス可塑性・学習を模倣する分子配線ニューラルネットワークへの取り組み," 応用物理学会 第10回集積化MEMS技術研究会, The University of Tokyo, Tokyo, Japan (May 20, 2016).
植吉 晃大, "制約付きボルツマンマシンのスケーラブル並列アーキテクチャとそのメモリエラー耐性," 東芝研究開発センター LSI基盤技術ラボラトリーセミナー, TOSHIBA Corporate Research & Development Center, Kawasaki, Japan (Mar. 22, 2016).
品田 高宏, 浅井 哲也, 東 悠介, 屋上 公二郎, "エマージングデバイス（ERD）：デバイス技術が進むべき道," 2015年度STRJワークショップ, Kokuyo Hall, Tokyo, Japan (Mar. 4, 2016).
Asai T., "Machine learning systems on FPGA/VLSI and their potential applications," CiNet Friday Lunch Seminar, NICT, Suita, Japan (Nov. 27, 2015).
Ushida M. and Asai T., "A self-organizing model of spatial patterns and its evaluation towards motion detection of textureless objects," CiNet Faculty Seminar, NICT, Suita, Japan (Sep. 14, 2015).
Asai T., "A Memristor ---the Fourth Fundamental Circuit Element--- and its Application to Unconventional Computation," The 6th IEEE International Nanoelectronics Conference 2014, Hokkaido University, Sapporo, Japan (Jul. 28-31, 2014).
Akai-Kasaya M., Tuan D.N., Asai T., Yamamoto S., Saito A., and Kuwahara Y., "Molecular neuromorphic learning systems consisting of synaptic devices on high-conductive polypyrrole films," CMOS Emerging Technologies Research 2014 Symposium, MINATEC, Grenoble, France (Jul. 7-8, 2014).
Gonzalez-Carabarin L. and Asai T., "Asynchronous digital circuits based on stochastic resonance for coarse-grained/low-voltage devices," CMOS Emerging Technologies Research 2014 Symposium, MINATEC, Grenoble, France (Jul. 7-8, 2014).
浅井 哲也, "雑音とばらつきを有効利用する機能電子回路," 次世代情報処理における揺らぎと確率, Saitama, Japan (Mar. 3-4, 2010).
浅井 哲也, "雑音と素子ばらつきを有効利用する生体模倣ハードウェア：ゆらぎは敵か味方か？," 電子情報通信学会ニューロコンピューティング研究会, Sapporo, Japan (Jan. 18-19, 2010).
浅井 哲也, "ゆらぎを積極的に利用する生体模倣集積回路," 平成21年度第三回ブレインウェア工学研究会, Sendai, Japan (Dec. 16, 2009).
Kikombo A.K. and Asai T., "Neuro-morphic circuit architectures employing temporal noises and device fluctuations to enhance signal-to-noise ratio in pulse-density modulation," Proceedings of the 4th International Workshop on Natural Computing, pp. 37-46, Himeji International Exchange Center, Himeji, Japan (Sep. 23-25, 2009).
浅井 哲也, "Emerging Research Architectures: 現状と今後の展望," 2007年度STRJワークショップ, Tokyo, Japan (Mar. 6-7, 2008).
Asai T. and Motoike I.N., "Turing-like reaction-diffusion patterns emerging on two-layered resistive sheets with nonlinear devices," The 2nd International Workshop on Natural Computing, Nagoya, Japan (Dec. 10-12, 2007).
浅井 哲也, "CMOSおよび量子ナノ構造による反応拡散デバイスとその応用," 産業技術総合研究所セミナー, Tsukuba, Japan (Oct. 12, 2004).
Adamatzky A. and Asai T., "Programming reaction-diffusion computers & the reaction-diffusion chip," Unconventional Programming Paradigms, Mont Saint-Michel, France (Sep. 15-17, 2004).
Asai T., "Reaction-diffusion systems on excitable semiconductor medium," 北海道大学理学研究科 数学専攻 NSCセミナー, Sapporo, Japan (Jul. 14, 2004).
Asai T., "Biomorphic analog devices based on reaction-diffusion systems," Proceedings of the 2004 Silicon Nanoelectronics Workshop, pp. 85-86, Hilton Hawaiian Village, Honolulu, U.S.A. (Jun. 13-14, 2004).
Asai T. and Amemiya Y., "Biomorphic analog circuits based on reaction-diffusion systems," Proceedings of the 33rd International Symposium on Multiple-Valued Logic, pp. 197-204, Meiji University, Tokyo, Japan (May 16-19, 2003).
Asai T., Hayasi H., and Amemiya Y., "Analog integrate-and-fire neurochips: neural competition in frequency and time domains," World Automation Congress 2002, IFMIP-037, Sheraton World Resort Orlando, Florida, U.S.A. (Jun. 9-13, 2002).
浅井 哲也, "非線形アナログ集積回路と反応拡散チップ：開発の現状とその応用," 第11回日本化学会「非線形反応と協同現象」研究会, Tokyo, Japan (Dec. 1-2, 2001).
国際会議
Kusunose R., Marukame T., and Uemura T., "Binary neural networks with giant conductance changes in Co2MnSi/MgO/Co2MnSi magnetic tunnel junctions," 2025 Joint MMM-Intermag Conference, Hyatt Regency, New Orleans, USA (Jan. 13-17, 2025).
Matsuno S., Abe Y., Ando K., and Asai T., "Physical reservoir computing on discrete analog CMOS circuits and its application to real data analysis and prediction," IEEE ICRC 2024, Carté Hotel , San Diego, USA (Dec. 16-17, 2024).
Kunimi T., Ando K., Marukame T., and Asai T., "Predictive coding networks consisting of analog electronic circuits based on the free-energy principle," The 27th SNU-HU Joint Symposium, Seoul National University, Seoul, Korea (Nov. 28, 2024).
Hori A., Arai F., Inoue Y., Marukame T., Asai T., and Ando K., "Variable-parallelism reconfigurable architecture for neural networks," The 27th SNU-HU Joint Symposium, Seoul National University, Seoul, Korea (Nov. 28, 2024).
Matsuno S., Abe Y., Ando K., and Asai T., "Numerical performance evaluation of analog electronic reservoir circuits with discrete CMOS devices," The 27th SNU-HU Joint Symposium, Seoul National University, Seoul, Korea (Nov. 28, 2024).
Tatsumi S., Ando K., and Asai T., "Replication of Physical Reservoir Computers," The 27th SNU-HU Joint Symposium, Seoul National University, Seoul, Korea (Nov. 28, 2024).
Minagawa K., Saito T., Kojima S., Ando K., and Asai T., "Out-of-distribution data detection using Bayesian convolutional neural network with variational inference," International Joint Conference on Neural Networks (IJCNN 2024), PACIFICO Yokohama, Yokohama, Japan (Jun. 30-Jul. 5, 2024).
Akeno I., Yamazaki H., Asai T., and Ando K., "Edge AI online training architecture using multi-phase-quantization optimizer," International Joint Conference on Neural Networks (IJCNN 2024), PACIFICO Yokohama, Yokohama, Japan (Jun. 30-Jul. 5, 2024).
Hagiwara N., Abe Y., and Asai T., "Highly-integrable analogue reservoir circuits based on a simple cycle architecture," The 5th International Symposium on Neuromorphic AI Hardware, RIHGA Royal Hotel Kokura, Kitakyushu, Japan (Mar. 1-2, 2024).
Minagawa K., Saito T., Kojima S., Ando K., and Asai T., "Out-of-distribution detection using Bayesian neural network toward hardware implementation," The 5th International Symposium on Neuromorphic AI Hardware, RIHGA Royal Hotel Kokura, Kitakyushu, Japan (Mar. 1-2, 2024).
Kunimi T., Hagiwara N., Ando K., and Asai T., "A novel dynamic predictive coding network with augmented direct feedback alignment towards its physical implementation," The 5th International Symposium on Neuromorphic AI Hardware, RIHGA Royal Hotel Kokura, Kitakyushu, Japan (Mar. 1-2, 2024).
Tatsumi S., Abe Y., Nishida K., and Asai T., "Physical reservoirs replication using a small-scale digital calibration reservoir," The 5th International Symposium on Neuromorphic AI Hardware, RIHGA Royal Hotel Kokura, Kitakyushu, Japan (Mar. 1-2, 2024).
Tamada K., Abe Y., and Asai T., "A resource-efficient streaming architecture of ensemble Kalman filters towards online learning for physical reservoir computing," The 5th International Symposium on Neuromorphic AI Hardware, RIHGA Royal Hotel Kokura, Kitakyushu, Japan (Mar. 1-2, 2024).
Akeno I., Yamazaki H., Asai T., and Ando K., "Edge AI online training architecture using multi-phase-quantization optimizer," The 5th International Symposium on Neuromorphic AI Hardware, RIHGA Royal Hotel Kokura, Kitakyushu, Japan (Mar. 1-2, 2024).
Hsiao W.-J., Asai T., Lu D., and Ando K., "A Novel Near-memory computing architecture for recurrent neural networks with SRAM and RRAM," The 5th International Symposium on Neuromorphic AI Hardware, RIHGA Royal Hotel Kokura, Kitakyushu, Japan (Mar. 1-2, 2024).
Kojima S., Minagawa K., Saito T., Ando K., and Asai T., "Acquisition of physical kinetics of machines by reservoir computing and its applications to anomaly detection," The 12th RIEC International Symposium on Brain Functions and Brain Computer, Research Institute of Electrical Communication, Tohoku University, Sendai, Japan (Feb. 27-28, 2024).
Yamakawa S., Ando K., and Asai T., "Evaluation of a nonlinear small signal detection circuit for a neuromorphic membrane using alginate gel," In-material Computing Workshop for Young Researchers, p. 16, PA-11, Hokkaido Jichiro Kaikan, Sapporo, Japan (Nov. 14, 2023).
Abe Y., Nishida K., Akai-Kasaya M., and Asai T., "Reservoir computing with high-order polynomial activation functions and regenerative Internal weights for enhancing nonlinear capacity and hardware resource efficiency," The 2023 International Symposium on Nonlinear Theory and Its Applications (NOLTA2023),, Cittadella Campus of the University, Catania, Italy (Sep. 26-29, 2023).
Yamakawa S., Ando K., Akai-Kasaya M., and Asai T., "A novel nonlinear small-signal detection circuit using divergence properties of second-order linear differential equations," Proceedings of the 5th International Conference on Microelectronics Devices & Technology (MicDAT' 2023), pp. 17-19, Pestana Casino Park Hotel, Funchal, Portugal (Sep. 20-22, 2023).
Hagiwara N., Asai T., Ando K., and Akai-Kasaya M., "Growth of 3D conductive polymer fiber networks towards neuromorphic wetware," Neuromorphic Organic Devices, Hotel Elbresidenz, Bad Schandau, Germany (Sep. 18-20, 2023).
Yamakawa S., Ando K., Akai-Kasaya M., and Asai T., "Design and evaluation of brain-computer communication devices using divergence properties of non-linear dynamical systems," The 9th Japan-Korea Joint Workshop on Complex Communication Sciences, Lahan Select, Gyeong Ju, Korea (Jan. 4-6, 2023).
Hagiwara N., Asai T., Ando K., and Akai-Kasaya M., "3D conductive polymer wiring synapses for neuromorphic wetware," The 4th International Symposium on Neuromorphic AI Hardware, ART HOTEL Kokura New Tagawa, Kitakyushu, Japan (Dec. 13-14, 2022).
Kaneko T., Momose H., and Asai T., "On-Device Training Architecture for Analog ReRAM Neural Networks with Digital BP," MEMRISYS 2022, Boston Marriott Cambridge Cambridge, Cambridge, USA (Nov. 30-Dec. 2, 2022).
Hagiwara N., Asai T., and Akai-Kasaya M., "Multi-synaptic conductance control using conductive polymer wiring," 2022 IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, USA (Jun. 11-12, 2022).
Nakada K., Suzuki S., Suzuki E., Terasaki Y., Sasaki T., and Asai T., "An information theoretic design for MEMS-based reservoir computing," The 2021 Nonlinear Science Workshop, Online (Dec. 6-8, 2021).
Sasaki Y., Muramatsu S., Nishida K., Akai-Kasaya M., and Asai T., "Digital implementation of a multilayer perceptron based on stochastic computing with online learning function," The 2021 Nonlinear Science Workshop, Online (Dec. 6-8, 2021).
Amemiya Y., Ali E.J., Hagiwara N., Akai-Kasaya M., and Asai T., "A heuristic model for configurable polymer-wire synaptic devices," The 2021 Nonlinear Science Workshop, Online (Dec. 6-8, 2021).
Ali E.J., Amemiya Y., Akai-Kasaya M., and Asai T., "Smart hardware architecture with random weight elimination and weight balancing algorithms," The 2021 Nonlinear Science Workshop, Online (Dec. 6-8, 2021).
Kubota H., Hasegawa T., Akai-Kasaya M., and Asai T., "On the noise sensitivity of physical reservoir computing in a ring array of atomic switches," The 2021 Nonlinear Science Workshop, Online (Dec. 6-8, 2021).
Hagiwara N., Okada M., Sugito Y., Asai T., Kuwahara Y., and Akai-Kasaya M., "Examination of machine learning using conductive polymer wires as nonvolatile resistance change elements," Dynamics Days 2020, Hilton Hartford, Hartford, USA (Jan. 3-5, 2020).
Ambalathankandy P., Ou Y., Kochiyil J., Takamaeda-Yamazaki S., Motomura M., Asai T., and Ikebe M., "Radiography contrast enhancement: smoothed LHE filter, a practical solution for digital X-rays with Mach band," 2019 International Conference on Digital Image Computing: Techniques and Applications, University of Western Australia, Perth, Australia (Dec. 2-4, 2019).
Okada M., Hikita W., Kuwahara Y., Asai T., and Akai-Kasaya M., "Building artificial Neural Network System composed of Growing Conductive Polymer," MANA International Symposium 2019, International Congress Center EPOCHAL TSUKUBA, Tsukuba, Japan (Mar. 4-6, 2019).
Kaneko T., Ikebe M., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Ternarized backpropagation: a hardware-oriented optimization algorithm for edge-oriented AI devices," The 7th RIEC International Symposium on Brain Functions and Brain Computer, Research Institute of Electrical Communication, Tohoku University, Sendai, Japan (Feb. 22-23, 2019).
Rim S., Suzuki S., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "Approach to reservoir computing with Schmitt trigger oscillator-based analog neural circuits," The 7th Japan-Korea Joint Workshop on Complex Communication Sciences, C5, Alpensia, Pyengonchang, Korea (Jan. 6-9, 2019).
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Dither NN: an accurate neural network with dithering for low bit-precision hardware," The 2018 International Conference on Field-Programmable Technology (FPT'18), Tenbusu-Naha Hall, Naha, Japan (Dec. 10-14, 2018).
Ambalathankandy P., Shimada T., Takamaeda-Yamazaki S., Motomura M., Asai T., and Ikebe M., "Analysis of smoothed LHE methods for processing images with optical illusions," IEEE International Conference on Visual Communications and Image Processing, Tempus Hotel Taichung , Taichung, Taiwan (Dec. 9-12, 2018).
Sasaki K., Okamoto S., Tashiro S., Asai T., and Kasai S., "Charge coupling between Polyoxometalate molecule and a GaAs-based nanowire for readout of molecular multiple charge state," The 31st International Microprocesses and Nanotechnology Conference, 15C-4-4, Sapporo Park Hotel, Sapporo, Japan (Nov. 13-16, 2018).
Kudo T., Ueyoshi K., Ando K., Hirose K., Uematsu R., Oba Y., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "Area and energy optimization for bit-serial log-quantized DNN Accelerator with shared accumulators," IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, Vietnam National University, Hanoi, Vietnam (Sep. 12-14, 2018).
Fujii T., Toi T., Tanaka T., Togawa K., Kitaoka T., Nishino K., Nakamura N., Nakahara H., and Motomura M., "New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications," 2018 Symposia on VLSI Technology and Circuits, pp. 41-42, Hilton Hawaiian Village, Hawaii, USA (Jun. 19-21, 2018).
Shimada T., Ikebe M., Ambalathankandy P., Takamaeda-Yamazaki S., Motomura M., and Asai T., "Sparse disparity estimation using global phase only correlation for stereo matching acceleration," 2018 IEEE International Conference on Acoustics, Speech and Signal Processing, Calgary Telus Convention Center, Alberta, Canada (Apr. 15-20, 2018).
Iwamaru N., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "A novel iris-center detection algorithm towards gaze estimation targeting molecular cellular automata," International Workshop on Molecular Architectonics 2018, P-25, Osaka University, Osaka, Japan (Mar. 2-3, 2018).
Sasaki K., Okamoto S., Tashiro S., Asai T., and Kasai S., "Characterization of stochastic charge dynamics of polyoxometalate dispersed on a GaAs-based nanowire FET," International Workshop on Molecular Architectonics 2018, P-22, Osaka University, Osaka, Japan (Mar. 2-3, 2018).
Okada M., Hikita W., Kuwahara Y., Asai T., and Akai-Kasaya M., "Complemental neural network built of growing polymer wire ," International Workshop on Molecular Architectonics 2018, P-24, Osaka University, Osaka, Japan (Mar. 2-3, 2018).
Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Kadomoto J., Miyata T., Hamada M., Kuroda T., and Motomura M., "QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS," 2018 International Solid-State Circuits Conference (ISSCC 2018), San Francisco Marriott Marquis, San Francisco, US (Feb. 11-15, 2018).
Hida I., Ueyoshi K., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "Sign-invariant unsupervised learning facilitates weighted-sum computation in analog neural-network devices," 2017 International Symposium on Nonlinear Theory and Its Applications, Cancun International Convention Center, Cancun, Mexico (Dec. 4-7, 2017).
Hirose K., Uematsu R., Ando K., Orimo K., Ueyoshi K., Ikebe M., Asai T., Takamaeda-Yamazaki S., and Motomura M., "Logarithmic Compression for Memory Footprint Reduction in Neural Network Training," 5th International Workshop on Computer Systems and Architectures (CSA 2017), Aomori Prefecture Tourist Center, Aomori, Japan (Nov. 19-22, 2017).
Tanibata A., Schmid A., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects (demo night)," The 27th International Conference on Field-Programmable Logic and Applications, Culture and Convention Center Het Pand, Ghent, Belgium (Sep. 4-8, 2017).
Ando K., Ueyoshi K., Hirose K., Orimo K., Yonekawa H., Sato S., Nakahara H., Ikebe M., Takamaeda-Yamazaki S., Asai T., Kuroda T., and Motomura M., "In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks," 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017), Tufts University, Boston, USA (Aug. 6-9, 2017).
Ando K., Ueyoshi K., Orimo K., Yonekawa H., Sato S., Nakahara H., Ikebe M., Asai T., Takamaeda-Yamazaki S., Kuroda T., and Motomura M., "BRein memory: a 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS," 2017 Symposia on VLSI Technology and Circuits, Rihga Royal Hotel, Kyoto, Japan (Jun. 5-8, 2017).
Ueyoshi K., Marukame T., Asai T., Motomura M., and Schmid A., "Feature extraction system using restricted Boltzmann machines on FPGA," 2017 IEEE International Symposium on Circuits & Systems, A4P-O, Baltimore Marriott Waterfront, Baltimore, USA (May 28-31, 2017).
Ueyoshi K., Ando K., Orimo K., Ikebe M., Asai T., and Motomura M., "Exploring optimized accelerator design for binarized convolutional neural networks," The 2017 International Joint Conference on Neural Networks, William A. Egan Civic and Convention Center, Alaska, USA (May 14-19, 2017).
Yamamoto K., Takamaeda-Yamazaki S., Ikebe M., Asai T., and Motomura M., "A scalable ising model implementation on an FPGA," COOL Chips 20, Yokohama Media & Communications Center, Yokohama, Japan (Apr. 19-21, 2017).
Fujii T., Sato S., Nakahara H., and Motomura M., "An FPGA realization of a deep convolutional neural network using a threshold neuron pruning," International Symposium on Applied Reconfigurable Computing, Delft University, Delft, Netherlands (Apr. 3-7, 2017).
Ando K., Ueyoshi K., Orimo K., Ikebe M., Takamaeda-Yamazaki S., Asai T., and Motomura M., "Throughput analysis of a data-flow reconfigurable array architecture for convolutional neural networks," The 5th RIEC International Symposium on Brain Functions and Brain Computer, Tohoku University, Sendai, Japan (Feb. 27-28, 2017).
Nakahara H., Yonekawa H., Iwamoto H., and Motomura M., "A batch normalization free binarized convolutional deep neural network on an FPGA," International Symposium on Field-Programmable Gate Array, Monterey Marriott Hotel, California, USA (Feb. 22-24, 2017).
Nakahara H., Yonekawa H., Sasao T., Iwamoto H., and Motomura M., "A memory-based realization of a binarized deep convolutional neural network," International Conference on Field-Programmable Technology, Jiangou Hotel, Xi'an, China (Dec. 7-9, 2016).
Kusano H., Ikebe M., Asai T., and Motomura M., "An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions," 2016 International Conference on Reconfigurable Computing and FPGAs, Iberostar Cancun hotel, Cancun, Mexico (Nov. 30-Dec. 2, 2016).
Orimo K., Ando K., Ueyoshi K., Ikebe M., Asai T., and Motomura M., "FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting," 2016 International Conference on Reconfigurable Computing and FPGAs, Iberostar Cancun hotel, Cancun, Mexico (Nov. 30-Dec. 2, 2016).
Tanibata A., Ushida M., Schmid A., Ikebe M., Asai T., and Motomura M., "A hardware cellular-automaton architecture for spatial pattern generation towards motion-vector estimation of textureless objects," 2016 International Symposium on Nonlinear Theory and its Applications, pp. 622-625, New Welcity Yugawara, Shizuoka, Japan (Nov. 27-30, 2016).
Hida I., Ikebe M., Asai T., and Motomura M., "A two-clock-cycle naive Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors," 2016 IEEE Asia Pacific Conference on Circuits and Systems, Ramada Plaza Jeju Hotel, Jeju, Korea (Oct. 25-28, 2016).
Asai T., Mori M., Itou T., Take Y., Ikebe M., Kuroda T., and Motomura M., "Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces," European Solid-State Circuits Conference 2016, Swisstech Convention Centre, Lausanne, Switzerland (Sep. 12-15, 2016).
Ueyoshi K., Marukame T., Asai T., Motomura M., and Schmid A., "Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in deep belief network," IEEE International Symposium on Circuits and Systems, Montreal Sheraton Center, Montreal, Canada (May 22-25, 2016).
Yamamoto K., Asai T., and Motomura M., "Hardware architecture for online frequent items mining with memory-efficient data structure," COOL Chips XIX, Yokohama Media & Communications Center, Yokohama, Japan (Apr. 20-22, 2016).
Hirashima R., Asai T., and Oya T., "Design of thermal-noise-harnessing neuromorphic nano-electronic circuit based on axon of neuron for single-molecule device," International Chemical Congress of Pacific Basin Societies 2015, Hawaii Convention Center, Honolulu, USA (Dec. 15-20, 2015).
Takano M., Asai T., and Oya T., "Design of nano-electronic neural-network associative memory circuit for single-molecule devices," International Chemical Congress of Pacific Basin Societies 2015, Hawaii Convention Center, Honolulu, USA (Dec. 15-20, 2015).
Ushida M., Ishimura K., Schmid A., Asai T., and Motomura M., "Motion vector estimation of textureless objects exploiting reaction-diffusion cellular automata," 2015 International Symposium on Nonlinear Theory and its Applications, pp. 85-88, City University of Hong Kong, Hong Kong, China (Dec. 1-4, 2015).
Ikebe M., Uchida D., Take Y., Someya M., Chikuda S., Matsuyama K., Asai T., Kuroda T., and Motomura M., "Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer," 2015 Symposia on VLSI Technology and Circuits, 4-1, Rihga Royal Hotel, Kyoto, Japan (Jun. 15-19, 2015).
Itou T., Mori M., Ikebe M., Asai T., Kuroda T., and Motomura M., "A new architecture for feature extraction to perform machine learning by using motion vectors and its implementation in an FPGA," Proceedings of the 2015 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, pp. 294-297, Universiti Teknologi Malaysia, Kuala Lumpur, Malaysia (Feb. 27-Mar. 2, 2015).
Fukuda E.S., Inoue H., Takenaka T., Kim D., Sadahisa T., Asai T., and Motomura M., "Achieving higher performance of memcached by caching at network interface," The 2014 International Conference on Field Programmable Technology, Parkyard Hotel, Shanghai, China (Dec. 10-12, 2014).
Tuan D.N., Akai-Kasaya M., Asai T., Saito A., and Kuwahara Y., "Study on Electropolymerization Micro-wiring System Imitating Axonal Growth of Artificial Neurons towards Machine Learning," 2nd International Symposium on the Functionality of Organized Nanostructures (FON'14), National Museum of Emerging Science and Innovation (Miraikan), Tokyo, Japan (Nov. 26-28, 2014).
Hida I., Kim D., Asai T., and Motomura M., "A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator," Proceedings of the Asian Solid-State Circuits Conference 2014, pp. 37-40, 85 Sky Tower Hotel, KaoHsiung, Taiwan (Nov. 10-12, 2014).
Kim D., Fukuda E.S., Sadahisa T., Asai T., and Motomura M., "Hardware architecture for accelerating key-value retrieval implemented on FPGA," The 3rd Japan-Korea Joint Workshop on Complex Communication Sciences, Paradise Hotel, Busan, Korea (Oct. 27-28, 2014).
Gonzalez-Carabarin L., Asai T., and Motomura M., "Dual-rail asynchronous pipeline based on stochastic resonance logic gates," Proceedings of the 2014 International Symposium on Nonlinear Theory and its Applications, pp. 85-88, Cinema of Bourbaki Panorama, Luzern, Switzerland (Sep. 14-18, 2014).
Ishimura K., Komuro K., Schmid A., Asai T., and Motomura M., "Stochastic resonance in a unidirectional network of nonlinear oscillators driven by internal noise," Proceedings of the 2014 International Symposium on Nonlinear Theory and its Applications, pp. 89-92, Cinema of Bourbaki Panorama, Luzern, Switzerland (Sep. 14-18, 2014).
Mori M., Itou T., Ikebe M., Asai T., Kuroda T., and Motomura M., "FPGA-based design for motion-vector estimation exploiting high-speed imaging and its application to machine learning," Proceedings of the 2014 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, pp. 145-148, Waikiki Beach Marriott Resort & Spa, Honolulu, U.S.A. (Feb. 28-Mar. 3, 2014).
Sanada Y., Ohata K., Ogaki T., Matsuyama K., Ohira T., Chikuda S., Igarashi M., Kuroda T., Ikebe M., Asai T., and Motomura M., "FPGA implementation of a memory-efficient stereo vision algorithm based on 1-D guided filtering," Proceedings of the 2014 International Conference on Circuits, Systems, and Control, pp. 25-30, Lindner Grand Hotel Beau Rivage, Interlaken, Switzerland (Feb. 22-24, 2014).
Uchida D., Ikebe M., Someya M., and Motohisa J., "Low-power single-slope ADC with time to digital converter for CMOS image sensor," The 16th SNU-HU Joint Symposium, Seoul National University, Seoul, Korea (Dec. 13, 2013).
Ohata K., Sanada Y., Ogaki T., Matsuyama K., Ohira T., Chikuda S., Igarashi M., Ikebe M., Asai T., Motomura M., and Kuroda T., "Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation," Proceedings of the 2013 IEEE International Conference on Electronics, Circuits, and Systems, pp. 169-172, Yas Viceroy Hotel, Abu Dhabi, UAE (Dec. 8-11, 2013).
Fukuda E.S., Takenaka T., Inoue H., Kawashima H., Asai T., and Motomura M., "High level synthesis with stream query to C parser: Eliminating hardware development difficulties for software developers," Proceedings of the 18th Workshop on Synthesis And System Integration of Mixed Information Technologies, pp. 310-315, Hotel Sapporo Garden Palace, Sapporo, Japan (Oct. 21-22, 2013).
Chikuda S., Ohira T., Sanada Y., Igarashi M., Ikebe M., Asai T., and Motomura M., "FPGA implementation of 60-FPS QVGA-to-VGA single-image super resolution," in Proc. of the 2013 International Conference on Solid State Devices and Materials, pp. 136-137, Hilton Fukuoka Sea Hawk, Fukuoka, Japan (Sep. 24-27, 2013).
Gonzalez-Carabarin L., Asai T., and Motomura M., "Towards asynchronous digital circuit design based on stochastic resonance," The 1st International Conference on Nanoenergy, Hotel Gio, Perugia, Italy (Jul. 10-13, 2013).
Ishimura K., Schmid A., Asai T., and Motomura M., "Image steganography on digital reaction-diffusion processor," Nonlinear Dynamics of Electronic Systems 2013, Palazzo Ateneo, Bari, Italy (Jul. 10-12, 2013).
Fukuda E.S., Kawashima H., Inoue H., Fujii T., Furuta K., Asai T., and Motomura M., "C-based adaptive stream processing on dynamically reconfigurable hardware: window join case study," The 9th International Symposium on Applied Reconfigurable Computing, Courtyard Marriott Los Angeles, Los Angeles, U.S.A. (Mar. 25-27, 2013).
Sanada Y., Ohira T., Chikuda S., Igarashi M., Ikebe M., Asai T., and Motomura M., "FPGA implementation of single-image super resolution based on frame-bufferless box filtering," Proceedings of the 2013 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, pp. 516-519, Courtyard King Kamehameha's Kona Beach Hotel, The Island of Hawaii, U.S.A. (Mar. 4-7, 2013).
Nakada K., Miura K., Asai T., and Tanaka H., "Dynamical systems design of nonlinear oscillators using phase reduction approach," 2012 IEEE Asia Pacific Conference on Circuits and Systems, The Splendor Hotel Kaohsiung, Kaohsiung, Taiwan (Dec. 2-5, 2012).
Gonzalez-Carabarin L., Asai T., and Motomura M., "Spike transmission in locally coupled excitable circuits enhanced by membrane-potential-dependent noise," Asia Conference on Nanoscience and Nanotechnology 2012, Crowne Plaza Lijiang Ancient Town, Yunnan, China (Sep. 7-10, 2012).
Gong X., Asai T., and Motomura M., "Spatio-temporal pattern formation on memristive reaction-diffusion systems," Asia Conference on Nanoscience and Nanotechnology 2012, Crowne Plaza Lijiang Ancient Town, Yunnan, China (Sep. 7-10, 2012).
Gonzalez-Carabarin L., Asai T., and Motomura M., "Noise impact on spike transmission through serially-connected electrical FitzHugh-Nagumo model with subthreshold and suprathreshold interconductances," The 16th International Conference On Cognitive and Neural Systems, Boston University, Boston, U.S.A. (May 30-Jun. 1, 2012).
Yoshida K., Asai T., and Motomura M., "A subthreshold memory cell utilizing nonlinear characteristics of positive-feedback operational transconductance amplifier," Proceedings of the 2011 Kyoto Workshop on NOLTA, p. 15, Kyoto University, Kyoto, Japan (Nov. 30, 2011).
Toi T., Awashima T., Motomura M., and Amano H., "Time and space-multiplexed compilation challenge for dynamically reconfigurable processors," Proceesings of the 54th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), P03_1039, Yonsei University Seoul, Seoul, Korea (Aug. 7-10, 2011).
Tovar G.M., Asai T., and Amemiya Y., "Array-enhanced stochastic resonance in a network of noisy neuromorhic circuits," Proceedings of the 17th International Conference on Neural Information Processing, pp. 188-196, Sydney, Australia (Nov. 22-25, 2010).
Akoh N., Asai T., Yanagida T., Kawai T., and Amemiya Y., "A ReRAM-based analog synaptic device having spike-timing-dependent plasticity," Nanoelectronics Days 2010, p. 19, Aachen, Germany (Oct. 4-7, 2010).
Akoh N., Asai T., Amemiya Y., Yanagida T., and Kawai T., "A behavioral model of unipolar resistive RAMs and its application to HSPICE integration," The 17th International Workshop on Oxide Electronics, #167, Hyogo, Japan (Sep. 19-22, 2010).
Utagawa A., Asai T., and Amemiya Y., "Stochastic resonance in a simple electric circuit having a double-well potential ---Circuit experiments with a single operational amplifier---," Proceedings of 2010 International Symposium on Nonlinear Theory and its Applications, pp. 55-59, Krakow, Poland (Sep. 5-8, 2010).
Iida T., Asai T., Amemiya Y., and Sano E., "An offset compensation method using subthreshold CMOS operational amplifiers for fully differential amplifiers," Integrated Circuits and Devices in Vietnam 2010, Ho Chi Minh, Vietnam (Aug. 16, 2010).
Utagawa A., Asai T., and Amemiya Y., "Stochastic resonance in neuromorphic semiconductor devices having a double-well potential," Proceedings of the 14th International Conference on Cognitive and Neural Systems, p. 86, Boston, U.S.A. (May 19-22, 2010).
Kikombo A.K., Asai T., and Amemiya Y., "Exploiting temporal noises and device fluctuations in enhancing fidelity of pulse-density modulator consisting of single-electron neural circuits," Proceedings of the 16th International Conference on Neural Information Processing, pp. 384-391, Bangkok, Thailand (Dec. 1-5, 2009).
Ueno K., Asai T., and Amemiya Y., "A 0.02-to-2-MHz tunable clock reference circuit for intermittent pulse generators," Proceedings of the 2009 IEEJ International Analog VLSI Workshop, pp. 5-10, Chiangmai, Thailand (Nov. 18-20, 2009).
Utagawa A., Asai T., and Amemiya Y., "A noise-driven neuromorphic pulse-density modulator: experimental results with discrete MOS devices," Proceedings of the 2009 International Symposium on Nonlinear Theory and its Applications, pp. 206-209, Sapporo, Japan (Oct. 18-21, 2009).
Kikombo A.K., Asai T., and Amemiya Y., "Pulse-density modulation with an ensemble of single-electron circuits employing neuronal heterogeneity to achieve high temporal resolution," Proceedings of the 4th International Conference on Nano-Networks, pp. 51-56, Luzern, Switzerland (Oct. 18-20, 2009).
Ueno K., Asai T., and Amemiya Y., "A 30-MHz 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop," Proceedings of the 35th European Solid-State Circuits Conference, pp. 392-395, Athens, Greece (Sep. 14-18, 2009).
Utagawa A., Asai T., and Amemiya Y., "Noise-induced phase synchronization among analogue oscillator circuits: Experimental results with discrete MOS devices," Proceedings of the 17th International Workshop on Nonlinear Dynamics of Electronic Systems, pp. 110-113, Rapperswil, Switzerland (Jun. 21-24, 2009).
Kikombo A.K., Asai T., Oya T., Schmid A., Leblebici Y., and Amemiya Y., "A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons," Proceedings of the 2009 International Joint Conference on Neural Networks, pp. 1600-1605, Atlanta, U.S.A. (Jun. 14-19, 2009).
Utagawa A., Asai T., and Amemiya Y., "High-fidelity neuromorphic pulse-sendity modulator based on a model of vestibulo-ocular reflex," Proceedings of the 13th International Conference on Cognitive and Neural Systems, p. 140, Boston, U.S.A. (May 27-30, 2009).
Ueno K., Asai T., and Amemiya Y., "Low-power clock reference circuit for intermittent operation of subthreshold LSIs," Proceedings of the 2009 International Symposium on Circuits and Systems, pp. 5-8, Taipei, Taiwan (May 24-27, 2009).
Tsugita Y., Ueno K., Hirose T., Asai T., and Amemiya Y., "On-chip PVT compensation techniques for low-voltage CMOS digital LSIs," Proceedings of the 2009 International Symposium on Circuits and Systems, pp. 1565-1568, Taipei, Taiwan (May 24-27, 2009).
Ueno K., Hirose T., Asai T., and Amemiya Y., "A 300 nW, 7 ppm/°C CMOS voltage reference circuit based on subthreshold MOSFETs," Proceedings of the 14th Asia and South Pacific Design Automation Conference, pp. 95-96, Yokohama, Japan (Jan. 19-22, 2009).
Ueno K., Hirose T., Asai T., and Amemiya Y., "A 46-ppm/°C temperature and process compensated current reference with on-chip threshold voltage monitoring circuit," Proceedings of the IEEE Asian Solid-State Circuits Conference 2008, pp. 161-164, Fukuoka, Japan (Nov. 3-5, 2008).
Yamada K., Asai T., and Amemiya Y., "Single-flux-quantum dual-rail logic circuits with asynchronous collision-based fusion gates," The 21st International Symposium on Superconductivity, FDP-26, Tsukuba, Japan (Oct. 27-29, 2008).
Yamada K., Asai T., and Amemiya Y., "Single-flux quantum circuits for digital cellular automata and analog reaction-diffusion computing," Proceedings of the 3rd International Workshop on Natural Computing, p. 85, Yokohama, Japan (Sep. 23, 2008).
Ueno K., Hirose T., Asai T., and Amemiya Y., "A 0.3-µW, 7 ppm/°C CMOS voltage reference circuit for on-chip process monitoring in analog circuits," Proceedings of the 34th European Solid-State Circuits Conference, pp. 398-401, Edinburgh, U.K. (Sep. 15-19, 2008).
Utagawa A., Asai T., Sahashi T., and Amemiya Y., "Stochastic resonance in retinomorphic neural networks with nonidentical photoreceptors and noisy McCulloch-Pitts neurons," Proceedings of the 2008 International Symposium on Nonlinear Theory and its Applications, pp. 124-127, Budapest, Republic of Hungary (Sep. 7-10, 2008).
Nakada K., Igarashi J., Asai T., Tateno K., Hayashi H., Ohtsubo Y., Miki T., and Yoshii K., "Stochastic synchronization and array-enhanced coherence resonance in a bio-inspired chemical sensor array," The 2008 IEEE 11th International Conference on Computational Science and Engineering, CSE-08-4, S.Paulo, Brazil (Jul. 16-18, 2008).
Ogawa T., Hirose T., Asai T., and Amemiya Y., "Low voltage operation of master-slave flip-flops for ultra-low power subthreshold LSIs," The International Conference on Electrical Engineering 2008, O-166, Okinawa, Japan (Jul. 6-10, 2008).
Kikombo A.K., Asai T., and Amemiya Y., "A neuromorphic circuit for motion detection with single-electron devices based on correlation neural networks," The 2008 IEEE Silicon Nanoelectronics Workshop, #P1-31, Honolulu, U.S.A. (Jun. 15-16, 2008).
Kikombo A.K., Schmid A., Asai T., Leblebici Y., and Amemiya Y., "Implementation of early vision model for edge extraction with single-slsecton devices," Proceedings of the 12th International Conference on Cognitive and Neural Systems, p. 125, Boston, U.S.A. (May 14-17, 2008).
Kikombo A.K., Schmid A., Asai T., Leblebici Y., and Amemiya Y., "Toward a single-electron image processor for edge detection based on the inner retina model," Proceedings of the 2008 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 267-270, Gold Coast, Australia (Mar. 6-8, 2008).
Kikombo A.K., Schmid A., Leblebici Y., Asai T., and Amemiya Y., "A bio-inspired image processor for edge detection with single-electron circuits," 2007 International Semiconductor Device Research Symposium, #TA3-04, Maryland, U.S.A. (Dec. 12-14, 2007).
Tovar G.M., Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "Analog CMOS circuits implementing neural segmentation model based on symmetric STDP learning," Proceedings of the 14th International Conference on Neural Information Processing, pp. 306-315, Kitakyushu, Japan (Nov. 13-16, 2007).
Ogawa T., Hirose T., Asai T., and Amemiya Y., "Threshold-logic systems consisting of subthreshold CMOS circuits," Proceedings of the 2007 IEEJ International Analog VLSI Workshop, pp. 78-83, Limerick, Ireland (Nov. 7-9, 2007).
Asai T. and Amemiya Y., "Single-flux quantum logic circuits exploiting collision-based fusion gates," Proceedings of the 20th International Symposium on Superconductivity, p. 327, Tsukuba, Japan (Nov. 5-7, 2007).
Utagawa A., Asai T., Hirose T., and Amemiya Y., "Noise-induced synchronization among sub-RF CMOS neural oscillators for skew-free clock distribution," Proceedings of the 2007 International Symposium on Nonlinear Theory and its Applications, pp. 329-332, Vancouver, Canada (Sep. 16-19, 2007).
Tovar G.M., Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "Neuromorphic CMOS circuits implementing a novel neural segmentation model based on symmetric STDP learning," Proceedings of the 2007 International Joint Conference on Neural Networks, pp. 897-901, Florida, U.S.A. (Aug. 12-17, 2007).
Kikombo A.K., Hirose T., Asai T., and Amemiya Y., "Multi-valued logic circuits consisting of single-electron devices," Proceedings of the 2007 Silicon Nanoelectronics Workshop, pp. 81-82, Kyoto, Japan (Jun. 10-11, 2007).
Ueno K., Hirose T., Asai T., and Amemiya Y., "Floating millivolt reference for PTAT current generation in subthreshold MOS LSIs," Proceedings of the 2007 IEEE International Symposium on Circuits and Systems, pp. 3748-3751, New Orleans, U.S.A. (May 27-30, 2007).
Asai T., Oya T., and Amemiya Y., "Single-electron circuits performing noise-tolerant pulse-density modulation based on neuromorphic architecture," Abstract of the Nanotech Northern Europe 2007, p. 79, Helsinki, Finland (Mar. 27-29, 2007).
Hirose T., Asai T., and Amemiya Y., "Pulsed neural networks consisting of single-flux-quantum spiking neurons," Program and Abstracts of the 19th International Symposium on Superconductivity, p. 329, Nagoya, Japan (Oct. 30-Nov. 1, 2006).
Utagawa A., Asai T., Hirose T., and Amemiya Y., "Noise shaping pulse-density modulation in inhibitory neural networks with noise-sensitive subthreshold neuron circuits," Abstracts of the 3rd International Conference of Brain-inspired Information Technology, p. 42, Kitakyushu, Japan (Sep. 27-29, 2006).
Nakada K., Asai T., and Hayashi H., "Burst synchronization in two pulse-coupled resonate-and-fire neuron circuits," IFIP Conference on Artificial Intelligence, Santiago, Chile (Aug. 21-24, 2006).
Ueno K., Hirose T., Asai T., and Amemiya Y., "A watchdog sensor for assuring the quality of various perishables with subthreshold CMOS circuits," Proceedings of the 2006 Symposia on VLSI Technology and Circuits, pp. 194-195, Honolulu, U.S.A. (Jun. 13-17, 2006).
Nakada K., Igarashi J., Asai T., and Hayashi H., "Noise effects on performance of signal detection in an analog VLSI resonate-and-fire neuron," 2006 IEEE International Symposium on Circuits and Systems, pp. 5183-5186, Island of Kos, Greece (May 21-24, 2006).
Utagawa A., Asai T., Hirose T., and Amemiya Y., "A neuromorphic LSI performing noise-shaping pulse-density modulation with ultralow-power subthreshold neuron circuits," Proceedings of the 10th International Conference on Cognitive and Neural Systems, p. 53, Boston, U.S.A. (May 17-20, 2006).
Hirose T., Matsuoka T., Taniguchi K., Asai T., and Amemiya Y., "Ultralow-power temperature-insensitive current reference circuit," Technical Program and Abstracts of the 4th IEEE Conference on Sensors, p. 186, California, U.S.A. (Oct. 31-Nov. 3, 2005).
Ueno K., Hirose T., Asai T., and Amemiya Y., "A CMOS watch-dog sensor for guaranteeing the quality of perishables," Technical Program and Abstracts of the 4th IEEE Conference on Sensors, p. 186, California, U.S.A. (Oct. 31-Nov. 3, 2005).
Hirose T., Asai T., and Amemiya Y., "Spiking neuron devices consisting of single-flux-quantum circuits," Program and Abstracts of the 18th International Symposium on Superconductivity, p. 327, Tsukuba, Japan (Oct. 24-26, 2005).
Kagaya R., Oya T., Asai T., and Amemiya Y., "Stochastic resonance in an ensemble of single-electron neuromorphic devices and its application to competitive neural networks," Proceedings of the 2005 International Symposium on Nonlinear Theory and its Applications, pp. 329-332, Bruges, Belgium (Oct. 18-21, 2005).
Oya T., Asai T., and Amemiya Y., "A single-electron reaction-diffusion device for computation of a Voronoi diagram," Proceedings of the VIIIth European Conference on Artificial Life, pp. 23-34, Kent, U.K. (Sep. 5-9, 2005).
Suzuki Y., Takayama T., Motoike I.N., and Asai T., "Striped and spotted pattern generation on reaction-diffusion cellular automata -- theory and LSI implementation --," Proceedings of the VIIIth European Conference on Artificial Life, pp. 47-58, Kent, U.K. (Sep. 5-9, 2005).
Nakada K., Asai T., Hirose T., and Amemiya Y., "Analog current-mode implementation of central pattern generator for robot locomotion," Proceedings of the International Joint Conference on Neural Networks 2005, pp. 639-644, Montreal, Canada (Jul. 31-Aug. 4, 2005).
Oya T., Asai T., Kagaya R., and Amemiya Y., "Noise performance of single-electron depressing synapses for neuronal synchrony detection," Proceedings of the International Joint Conference on Neural Networks 2005, pp. 2849-2854, Montreal, Canada (Jul. 31-Aug. 4, 2005).
Kamiya T., Motoike I.N., and Asai T., "Spatial pattern formation of diffusive Lotka-Volterra system on analog integrated circuits," Proceedings of the XXV Dynamics Days Europe, pp. 60-61, Berlin, Germany (Jul. 25-28, 2005).
Oya T., Asai T., and Amemiya Y., "A single-electron device for computational geometry -- constructing the Voronoi diagram by means of single-electron circuits," Proceedings of the 2005 Silicon Nanoelectronics Workshop, pp. 128-129, Kyoto, Japan (Jun. 12-13, 2005).
Oya T., Schmid A., Asai T., Leblebici Y., and Amemiya Y., "Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2535-2538, Kobe, Japan (May 23-26, 2005).
Nakada K., Asai T., Hirose T., and Amemiya Y., "Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1923-1926, Kobe, Japan (May 23-26, 2005).
Kagaya R., Oya T., Asai T., and Amemiya Y., "Stochastic resonance in an emsemble of single-electron neuromorphic devices," Proceedings of the 9th International Conference on Cognitive and Neural Systems, II-#28, Boston, U.S.A. (May 18-21, 2005).
Oya T., Asai T., Kagaya R., Hirose T., and Amemiya Y., "Neuromorphic single-electron circuit and its application to temporal-domain neural competition," Proceedings of the 2004 International Symposium on Nonlinear Theory and its Application, pp. 235-239, Fukuoka, Japan (Nov. 29-Dec. 3, 2004).
Takahashi M., Oya T., Hirose T., Asai T., and Amemiya Y., "A CMOS reaction-diffusion device using minority-carrier diffusion in seminonductors," Proceedings of the 2004 International Symposium on Nonlinear Theory and its Application, pp. 601-605, Fukuoka, Japan (Nov. 29-Dec. 3, 2004).
Oya T., Asai T., Kagaya R., Hirose T., and Amemiya Y., "A competitive neural network with neuromorphic single-electron circuits," Proceedings of the 5th International Conference on Biological Physics, B09-342, Gothenburg, Sweden (Aug. 23-27, 2004).
Asai T., Kanazawa Y., Hirose T., and Amemiya Y., "A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection," Proceedings of the 2004 International Joint Conference on Neural Networks , W107, Budapest, Hungary (Jul. 25-29, 2004).
Oya T., Asai T., and Amemiya Y., "A single-electron device for an analog computation," Proceedings of the 2004 Silicon Nanoelectronics Workshop, pp. 123-124, Honolulu, U.S.A. (Jun. 13-14, 2004).
Nakada K., Asai T., and Amemiya Y., "An analog CMOS circuit implementing a CNN-based locomotion controller for quadruped walking robots," Proceedings of the 2004 IEEE International Symposium on Circuits and Systems , vol. 3, pp. 1-4, Vancouver, Canada (May 23-26, 2004).
Asai T., Kanazawa Y., Ikebe M., and Amemiya Y., "A Neuromorphic CMOS Family and its Application," International Symposium on Bio-Inspired Systems, P8-5, Kitakyushu, Japan (Mar. 7-9, 2004).
Nakada K., Asai T., and Amemiya Y., "A novel analog cellular neural network for biologically-inspired walking robot," The 46th IEEE Midwest Symposium on Circuits and Systems , 576N, Cairo, Egypt (Dec. 27-30, 2003).
Nakada K., Asai T., and Amemiya Y., "An analog neural oscillator circuit for locomotion control in quadruped walking robot," Proceedings of the 2003 International Joint Conference on Neural Networks , vol. 2, pp. 983-988, Oregon, U.S.A. (Jul. 20-24, 2003).
Oya T., Ueno T., Asai T., and Amemiya Y., "Reaction-diffusion systems using single-electron oscillators," Abstract of the 2003 Silicon Nanoelectronics Workshop, pp. 82-83, Kyoto, Japan (Jun. 8-9, 2003).
Takahasi Y., Oya T., Asai T., and Amemiya Y., "A single-electron oscillator with a multiple tunneling junction," Abstract of the 2003 Silicon Nanoelectronics Workshop, pp. 98-99, Kyoto, Japan (Jun. 8-9, 2003).
Kanazawa Y., Yamada T., Asai T., and Amemiya Y., "Wireless synaptic / neuro devices based on interactions of local electric-fields and CDMA communication technology," 2002 IEEE International Conference on Systems, Man and Cybernetics, WA1P3, Hammamet, Tunisia (Oct. 6-9, 2002).
Oya T., Asai T., Fukui T., and Amemiya Y., "A majority-logic device using a single-electron box," Proceedings of the 2002 Silicon Nanoelectronics Workshop, pp. 79-80, Honolulu, U.S.A. (Jun. 9-10, 2002).
Yamada T., Asai T., and Amemiya Y., "An excitable membrane device using minority carrier transport in semiconductors," Proceedings of the 6th International Conference on Cognitive and Neural Systems, II-#37, Boston, U.S.A. (May 29-Jun. 1, 2002).
Asai T. and Amemiya Y., "Frequency- and temporal-domain neural competition in analog integrate-and-fire neurochips," Proceedings of the 2002 International Joint Conference on Neural Networks, pp. 1337-1341, Honolulu, U.S.A. (May 12-17, 2002).
Asai T., Nishimiya Y., and Amemiya Y., "A novel reaction-diffusion system based on minority-carrier transport in solid-state CMOS devices," Proceedings of the International Semiconductor Device Research Symposium, pp. 141-144, Washington DC, U.S.A. (Dec. 5-7, 2001).
Nishimiya Y., Sunayama T., Asai T., and Amemiya Y., "Reaction-diffusion chip based on cellular-automaton processing," Proceedings of the International Symposium on Nonlinear Theory and its Applications, vol. 2, pp. 593-596, Miyagi, Japan (Oct. 28-Nov. 1, 2001).
Kato H., Asai T., and Amemiya Y., "Reaction-diffusion neuro chips: analog CMOS implementation of locally coupled Wilson-Cowan oscillators," Proceedings of the 5th International Conference on Cognitive and Neural Systems, II-#41, Boston, U.S.A. (May 30-Jun. 2, 2001).
Koutani M., Asai T., and Amemiya Y., "Analog-digital CMOS circuits for motion detection with direction-selective neural networks," Proceedings of the 7th International Conference on Neural Information Processing, vol. 1, pp. 624-629, Taejon, Korea (Nov. 14-18, 2000).
Asai T., Koutani M., and Amemiya Y., "An analog-digital hybrid CMOS circuit for two-dimensional motion detection with correlation neural networks," Proccedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, vol. 3, pp. 494-499, Como, Italy (Jul. 24-27, 2000).
Kasaya M., Yasuda H., and Mori H., "HREM and optical absorption spectroscopy analysis of AlSb clusters formed by spontaneous alloying of antimony atoms into indium-cored alclusters," 14th International Congress on Electron Microscopy, Cancun, Mexco (Aug. 31-Sep. 4, 1998).
Kan S., "Novel architecture design of echo state network and performance analysis of information processing," 第10回分子アーキテクトニクス研究会 - 若手優秀講演賞, 2019年11月8日.
Rim S., Suzuki S., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T., "Approach to reservoir computing with Schmitt trigger oscillator-based analog neural circuits," JKCCS 2019 - Best Paper Award, Jan. 8, 2019.
Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda S., and Motomura M., "Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware," FPT'18 - Best Paper Award, Dec. 13, 2018.
Ueyoshi K., "QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS," IEEE SSCS - Predoctoral Achievement Award, Dec. 1, 2018.
Ueyoshi K., Ando K., Hirose K., Takamaeda-Yamazaki S., Kadomoto J., Miyata T., Hamada M., Kuroda T., and Motomura M., "QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS," ISSCC 2018 Silkroad Award, Feb. 11, 2018.
Kan Shaohua, 中嶋 浩平, 浅井 哲也, 赤井 恵, "A physical system that enables reservoir computing through electrochemical reactions," In-Materio Neuromorphic Computing, Nambu Yoichiro Hall, Osaka University, (On line), 2022年7月27日.
Kan Shaohua, 中嶋 浩平, 浅井 哲也, 赤井 恵, "Availability of nonlinear response of materials using in the construction of simple reservoir computing," 第81回応用物理学会秋季学術講演会, 9p-Z28-11, (オンライン開催), 2020年9月8-11日.
Kan Shaohua, 中嶋 浩平, 浅井 哲也, 赤井 恵, "Availability of nonlinear response of materials using in the construction of simple reservoir computing," 電子情報通信学会複雑コミュニケーションサイエンス研究会, (オンライン開催), 2020年8月3-4日.
Kan Shaohua, 中嶋 浩平, 浅井 哲也, 赤井 恵, "Novel architecture design of echo state network and performance analysis of information processing," 第10回分子アーキテクトニクス研究会, P-24, 九州国立博物館, (福岡), 2019年11月7-8日.
