北海道大学 大学院情報科学研究院

卒業生とその進路

導電性ポリマーワイヤー成長の簡易数理モデルとその脳型デバイス応用に関する研究


雨宮 佳希

2021 年度 卒 ／修士（情報科学）

修士論文の概要

本研究は、様々なニューラルネットワークに対して高い実装効率の維持し低消費電力を可能にするアーキテクチャを求めるものである。近年精力的に研究されてるAI専用ハードウェアのアーキテクチャとして2Dクロスバーモデルがあるが、このモデルは全結合型ニューラルネットワークに対応しているため畳み込みなどの近傍結合を表現する場合に無駄が生じる。そこで、次元の障壁を超えるべく立体的な新しいアーキテクチャのシナプス素子が望まれている。我々は新しいアーキテクチャについて、CBRAMから着想を得た。CBRAMに電流を流すと電位勾配に沿って電極間に導電性フィラメントが発生し配線が形成されるため、導電性フィラメントが発生を電極点の間で制御することで無次元の配線を理論的に可能とする。そんなCBRAMを立体的に集積することで実際の脳構造を模した脳型デバイスを、我々は新しいAI専用ハードウェアとして提案する。我々のチームが研究しているCBRAMはPEDOT:PSSであり、前駆体溶液とそれに浸した電極に矩形波交流ポテンシャルを印加することで、電解重合により導電性高分子PEDOT:PSSワイヤーが発生する。本研究ではこのPEDOT:PSSワイヤー成長のヒューリスティックモデルを考案しシミュレータを作成・応用することで予め三次元的な電極配置による実験で起こる問題を予見することを最終目標とする。まず最初に、PEDOT:PSSワイヤー成長の特徴を「量子化した溶液空間内で最も電流が流れた場所を、導電性ポリマーワイヤーに変化させる」という形に単純化し、これを基本原理に2次元シミュレータを作成した。2次元シミュレーションは成功しヒューリスティックモデルを用いたニューラルネットワークの学習可能性を示した。次に二次元シミュレータを三次元へ拡張した。電位分布の解析方法に二次元シミュレータでは節点法を用いたが、三次元への拡張でシミュレータの規模が増大したことに対処するため、電位分布の解析方法をオイラー法に変更した。三次元シミュレーションも成功したがシミュレーションを行う中で、シミュレーションで再現する空間の規模とシミュレーション時間がトレードオフの関係にあり、さらに複雑なシミュレーションを行うためにはこの関係が肝要であることがわかった。

学術論文

  1. Amemiya Y., Ali E.J., Hagiwara N., Akai-Kasaya M., and Asai T., "Heuristic model for configurable polymer wire synaptic devices," Nonlinear Theory and Its Applications, vol. E13-N, no. 2, pp. 379-384 (2022).
  2. Ali E.J., Amemiya Y., Akai-Kasaya M., and Asai T., "Smart hardware architecture with random weight elimination and weight balancing algorithms," Nonlinear Theory and Its Applications, vol. E13-N, no. 2, pp. 336-342 (2022).
  3. Takahagi K., Matsushita H., Iida T., Ikebe M., Amemiya Y., and Sano E., "Low-power wake-up receiver with subthreshold CMOS circuits for wireless sensor networks," Analog Integrated Circuits and Signal Processing, vol. 75, no. 2, pp. 199-205 (2013).
  4. Utagawa A., Asai T., and Amemiya Y., "Noise-induced phase synchronization among analog MOS oscillator circuits," Fluctuation and Noise Letters, vol. 11, no. 2, pp. 1250007/1-11 (2012).
  5. Utagawa A., Asai T., and Amemiya Y., "Stochastic resonance in simple analog circuits with a single operational amplifier having a double-well potential," Nonlinear Theory and Its Applications, vol. 2, no. 4, pp. 409-416 (2011).
  6. Utagawa A., Asai T., and Amemiya Y., "High-fidelity pulse density modulation in neuromorphic electric circuits utilizing natural heterogeneity," Nonlinear Theory and Its Applications, vol. 2, no. 2, pp. 218-225 (2011).
  7. Fujita D., Asai T., and Amemiya Y., "A neuromorphic MOS circuit imitating jamming avoidance response of Eigenmannia," Nonlinear Theory and Its Applications, vol. 2, no. 2, pp. 205-217 (2011).
  8. Kikombo A.K., Asai T., and Amemiya Y., "Neuro-morphic circuit architectures employing temporal noises and device fluctuations to improve signal-to-noise ratio in a single-electron pulse-density modulator," International Journal of Unconventional Computing, vol. 7, no. 1-2, pp. 53-64 (2011).
  9. Ueno K., Asai T., and Amemiya Y., "Low-power temperature-to-frequency converter consisting of subthreshold CMOS circuits for integrated smart temperature sensors," Sensors and Actuators A: Physical, vol. 165, no. 1, pp. 132-137 (2011).
  10. Akoh N., Asai T., Yanagida T., Kawai T., and Amemiya Y., "A behavioral model of unipolar resistive RAMs and its application to HSPICE integration," IEICE Electronics Express, vol. 7, no. 19, pp. 1467-1473 (2010).
  11. Ueno K., Hirose T., Asai T., and Amemiya Y., "A 1-uW, 600-ppm/°C current reference circuit consisting of subthreshold CMOS circuits," IEEE Transactions on Circuits and Systems II, vol. 57, no. 9, pp. 681-685 (2010).
  12. Tsugita Y., Ueno K., Hirose T., Asai T., and Amemiya Y., "An on-chip PVT compensation technique with current monitoring circuit for low-voltage CMOS digital LSIs," IEICE Transactions on Electronics, vol. E93-C, no. 6, pp. 835-841 (2010).
  13. Asai S., Ueno K., Asai T., and Amemiya Y., "High-resistance resistor consisting of a subthreshold CMOS differential pair," IEICE Transactions on Electronics, vol. E93-C, no. 6, pp. 741-746 (2010).
  14. Hirai T., Asai T., and Amemiya Y., "CMOS phase-shift oscillator based on the conduction of heat," Journal of Circuits, Systems, and Computers, vol. 19, no. 4, pp. 763-772 (2010).
  15. Ueno K., Hirose T., Asai T., and Amemiya Y., "Low-voltage process-compensated VCO with on-chip process monitoring and body-biasing circuit techniques," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no. 12, pp. 3079-3081 (2009).
  16. Utagawa A., Sahashi T., Asai T., and Amemiya Y., "Stochastic resonance in an array of locally-coupled McCulloch-Pitts neurons with population heterogeneity," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no. 10, pp. 2508-2513 (2009).
  17. Kikombo A.K., Tabe M., and Amemiya Y., "Photon position sensor consisting of single-electron circuits," Nanotechnology, vol. 20, no. 40, pp. 405209/1-7 (2009).
  18. Ueno K., Hirose T., Asai T., and Amemiya Y., "A 300-nW, 15-ppm/°C, 20-ppm/V CMOS voltage reference circuit consisting of subthreshold MOSFETs," IEEE Journal of Solid-State Circuits, vol. 44, no. 7, pp. 2047-2054 (2009).
  19. Kikombo A.K., Asai T., Oya T., Schmid A., Leblebici Y., and Amemiya Y., "A neuromorphic single-electron circuit for noise-shaping pulse-density modulation," International Journal of Nanotechnology and Molecular Computation, vol. 1, no. 2, pp. 80-92 (2009).
  20. Hirose T., Hagiwara A., Asai T., and Amemiya Y., "A highly sensitive thermosensing CMOS circuit based on self-biasing circuit technique," IEEJ Transactions on Electrical and Electronic Engineering, vol. 4, no. 2, pp. 278-286 (2009).
  21. Kikombo A.K., Schmid A., Asai T., Leblebici Y., and Amemiya Y., "A bio-inspired image processor for edge detection with single-electron circuits," Journal of Signal Processing, vol. 13, no. 2, pp. 133-144 (2009).
  22. Ogawa T., Hirose T., Asai T., and Amemiya Y., "Threshold-logic devices consisting of subthreshold CMOS circuits," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no. 2, pp. 436-442 (2009).
  23. Kikombo A.K., Asai T., and Amemiya Y., "An elementary neuro-morphic circuit for visual motion detection with single-electron devices based on correlation neural networks," Journal of Computational and Theoretical Nanoscience, vol. 6, no. 1, pp. 89-95 (2009).
  24. Asai T., Yamada K., and Amemiya Y., "Single-flux quantum logic circuits exploiting collision-based fusion gates," Physica C, vol. 468, no. 15-20, pp. 1983-1986 (2008).
  25. Utagawa A., Asai T., Hirose T., and Amemiya Y., "Noise-induced synchronization among sub-RF CMOS analog oscillators for skew-free clock distribution," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 9, pp. 2475-2481 (2008).
  26. Kikombo A.K., Hirose T., Asai T., and Amemiya Y., "Non-linear phenomena in electronic systems consisting of coupled single-electron oscillators," Chaos, Solitons and Fractals, vol. 37, no. 1, pp. 100-107 (2008).
  27. Hirose T., Asai T., and Amemiya Y., "Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs," IEICE Electronics Express, vol. 5, no. 6, pp. 204-210 (2008).
  28. Tovar G.M., Asai T., Hirose T., and Amemiya Y., "Critical temperature sensor based on oscillatory neuron models," Journal of Signal Processing, vol. 12, no. 1, pp. 17-24 (2008).
  29. Tovar G.M., Asai T., Fujita D., and Amemiya Y., "Analog MOS circuits implementing a temporal coding neural model," Journal of Signal Processing, vol. 12, no. 6, pp. 423-432 (2008).
  30. Yamada K., Asai T., Hirose T., and Amemiya Y., "On digital LSI circuits exploiting collision-based fusion gates," International Journal of Unconventional Computing, vol. 4, no. 1, pp. 45-59 (2008).
  31. Nakada K., Asai T., Hirose T., Hayashi H., and Amemiya Y., "A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters," Neurocomputing, vol. 71, no. 1-3, pp. 3-12 (2007).
  32. Utagawa A., Asai T., Hirose T., and Amemiya Y., "An inhibitory neural-network circuit exhibiting noise shaping with subthreshold MOS neuron circuits," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 10, pp. 2108-2115 (2007).
  33. Hirose T., Asai T., and Amemiya Y., "Pulsed neural networks consisting of single-flux-quantum spiking neurons," Physica C, vol. 463-465, no. 1, pp. 1072-1075 (2007).
  34. Kikombo A.K., Oya T., Asai T., and Amemiya Y., "Discrete dynamical systems consisting of single-electron circuits," International Journal of Bifurcation and Chaos, vol. 17, no. 10, pp. 3613-3617 (2007).
  35. Fukuda E.S., Tovar G.M., Asai T., Hirose T., and Amemiya Y., "Neuromorphic CMOS circuits implementing a novel neural segmentation model based on symmetric STDP learning," Journal of Signal Processing, vol. 11, no. 6, pp. 439-444 (2007).
  36. Takahashi M., Asai T., Hirose T., and Amemiya Y., "A CMOS reaction-diffusion device using minority-carrier diffusion in semiconductors," International Journal of Bifurcation and Chaos, vol. 17, no. 5, pp. 1713-1719 (2007).
  37. Oya T., Asai T., and Amemiya Y., "Stochastic resonance in an ensemble of single-electron neuromorphic devices and its application to competitive neural networks," Chaos, Solitons and Fractals, vol. 32, no. 2, pp. 855-861 (2007).
  38. Ueno K., Hirose T., Asai T., and Amemiya Y., "CMOS smart sensor for monitoring the quality of perishables," IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 798-803 (2007).
  39. Oya T., Asai T., and Amemiya Y., "A single-electron reaction-diffusion device for computation of a Voronoi diagram," International Journal of Unconventional Computing, vol. 3, no. 4, pp. 271-284 (2007).
  40. Hirose T., Asai T., and Amemiya Y., "Power-supply circuits for ultralow-power subthreshold MOS-LSIs," IEICE Electronics Express, vol. 3, no. 22, pp. 464-468 (2006).
  41. (invited paper) Amemiya Y., "Single-electron logic systems based on a graphical representation of digital functions," IEICE Transactions on Electronics, vol. E89-C, no. 11, pp. 1504-1511 (2006).
  42. Hirose T., Asai T., and Amemiya Y., "Spiking neuron devices consisting of single-flux-quantum circuits," Physica C, vol. 445-448, no. N/A, pp. 1020-1023 (2006).
  43. Tovar G.M., Hirose T., Asai T., and Amemiya Y., "Neuromorphic MOS circuits exhibiting precisely-timed synchronization with silicon spiking neurons and depressing synapses," Journal of Signal Processing, vol. 10, no. 6, pp. 391-397 (2006).
  44. Yamada K., Motoike I.N., Asai T., and Amemiya Y., "Design methodologies for compact logic circuits based on collision-based computing," IEICE Electronics Express, vol. 3, no. 13, pp. 292-298 (2006).
  45. Ueno K., Hirose T., Asai T., and Amemiya Y., "A CMOS watchdog sensor for certifying the quality of various perishables with a wider activation energy," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 4, pp. 902-907 (2006).
  46. Oya T., Asai T., Kagaya R., Hirose T., and Amemiya Y., "Neuronal synchrony detection on single-electron neural networks," Chaos, Solitons and Fractals, vol. 27, no. 4, pp. 887-894 (2006).
  47. Asai T., Kamiya T., Hirose T., and Amemiya Y., "A subthreshold analog MOS circuit for Lotka-Volterra chaotic oscillator," International Journal of Bifurcation and Chaos, vol. 16, no. 1, pp. 207-212 (2006).
  48. Hirose T., Matsuoka T., Taniguchi K., Asai T., and Amemiya Y., "Ultralow-power current reference circuit with low temperature dependence," IEICE Transactions on Electronics, vol. E88-C, no. 6, pp. 1142-1147 (2005).
  49. Nakada K., Asai T., and Amemiya Y., "Analog CMOS implementation of a CNN-based locomotion controller with floating-gate devices," IEEE Transactions on Circuits and Systems I, vol. 52, no. 6, pp. 1095-1103 (2005).
  50. Asai T., Ikebe M., Hirose T., and Amemiya Y., "A quadrilateral-object composer for binary images with reaction-diffusion cellular automata," International Journal of Parallel, Emergent and Distributed Systems, vol. 20, no. 1, pp. 57-68 (2005).
  51. Oya T., Schmid A., Asai T., Leblebici Y., and Amemiya Y., "On the fault tolerance of a clustered single-electron neural network for differential enhancement," IEICE Electronics Express, vol. 2, no. 3, pp. 76-80 (2005).
  52. Oya T., Asai T., Fukui T., and Amemiya Y., "Reaction-diffusion systems consisting of single-electron oscillators," International Journal of Unconventional Computing, vol. 1, no. 2, pp. 177-194 (2005).
  53. Asai T., Kanazawa Y., Hirose T., and Amemiya Y., "Analog reaction-diffusion chip imitating the Belousov-Zhabotinsky reaction with hardware Oregonator model," International Journal of Unconventional Computing, vol. 1, no. 2, pp. 123-147 (2005).
  54. Nakada K., Asai T., and Amemiya Y., "Biologically-inspired locomotion controller for a quadruped walking robot: Analog IC implementation of a CPG-based controller," Journal of Robotics and Mechatronics, vol. 16, no. 4, pp. 397-403 (2004).
  55. Matsubara H., Asai T., Hirose T., and Amemiya Y., "Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata," IEICE Electronics Express, vol. 1, no. 9, pp. 248-252 (2004).
  56. Kanazawa Y., Asai T., Hirose T., and Amemiya Y., "A MOS circuit for bursting neural oscillators with excitable Oregonators," IEICE Electronics Express, vol. 1, no. 4, pp. 73-76 (2004).
  57. Kagaya R., Ikebe M., Asai T., and Amemiya Y., "On-chip fixed-pattern-noise canceling with non-destructive intermediate readout circuitry for CMOS active-pixel sensors," WSEAS Transactions on Circuits and Systems, vol. 3, no. 3, pp. 477-479 (2004).
  58. Asai T., Adamatzky A., and Amemiya Y., "Towards reaction-diffusion computing devices based on minority-carrier transport in semiconductors," Chaos, Solitons and Fractals, vol. 20, no. 4, pp. 863-876 (2004).
  59. Nakada K., Asai T., and Amemiya Y., "Design of an artificial central pattern generator with feedback controller," Intelligent Automation and Soft Computing, vol. 10, no. 2, pp. 185-192 (2004).
  60. Kanazawa Y., Asai T., Ikebe M., and Amemiya Y., "A novel CMOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection," International Journal of Robotics and Automation, vol. 19, no. 4, pp. 206-212 (2004).
  61. Oya T., Takahashi Y., Ikebe M., Asai T., and Amemiya Y., "A single-electron circuit as a discrete dynamical system," Superlattices and Microstructures, vol. 34, no. 3-6, pp. 253-258 (2003).
  62. Nakada K., Asai T., and Amemiya Y., "An analog central pattern generator for interlimb coordination in quadruped locomotion," IEEE Transactions on Neural Networks, vol. 14, no. 5, pp. 1356-1365 (2003).
  63. Asai T., Kanazawa Y., and Amemiya Y., "A subthreshold MOS neuron circuit based on the Volterra system," IEEE Transactions on Neural Networks, vol. 14, no. 5, pp. 1308-1312 (2003).
  64. Kanazawa Y., Asai T., and Amemiya Y., "Basic circuit design of a neural processor: analog CMOS implementation of spiking neurons and dynamic synapses," Journal of Robotics and Mechatronics, vol. 15, no. 2, pp. 208-218 (2003).
  65. Oya T., Asai T., and Amemiya Y., "Single electron logic device with simple structure," 重複_Electronics Letters, vol. 39, no. 13, pp. 965-967 (2003).
  66. Oya T., Asai T., Fukui T., and Amemiya Y., "A majority-logic device using an irreversible single-electron box," IEEE Transactions on Nanotechnology, vol. 2, no. 1, pp. 15-22 (2003).
  67. Asai T., Nishimiya Y., and Amemiya Y., "A CMOS reaction-diffusion circuit based on cellular-automaton processing emulating the Belousov-Zhabotinsky reaction," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E85-A, no. 9, pp. 2093-2096 (2002).
  68. Oya T., Asai T., Fukui T., and Amemiya Y., "A majority-logic nanodevice using a balanced pair of single-electron boxes," Journal of Nanoscience and Nanotechnology, vol. 2, no. 3/4, pp. 333-342 (2002).
  69. Inokuchi T., Yamada T., Asai T., and Amemiya Y., "Analog computation using quantum-flux parametron devices," Physica C, vol. 357-360, no. 2, pp. 1618-1621 (2001).
  70. Yamada T., Kinoshita Y., Kasai S., Hasegawa H., and Amemiya Y., "Quantum-dot logic circuits based on the shared binary decision diagram," Japanese Journal of Applied Physics, vol. 40, no. 7, pp. 4485-4488 (2001).
  71. Asai T., Sunayama T., Amemiya Y., and Ikebe M., "A MOS vision chip based on the cellular-automaton processing," Japanese Journal of Applied Physics, vol. 40, no. 4B, pp. 2585-2592 (2001).
  72. Yamada T., Akazawa M., Asai T., and Amemiya Y., "Boltzmann-machine neural network devices using single-electron tunnelling," Nanotechnology, vol. 12, no. 1, pp. 60-67 (2001).
  73. Tokuda E., Asahi N., Yamada T., and Amemiya Y., "Analog computation using single-electron circuits," Analog Integrated Circuits and Signal Processing, vol. 24, no. 1, pp. 41-49 (2000).
  74. Akazawa M., Tokuda E., Asahi N., and Amemiya Y., "Quantum Hopfield network using single-electron circuits --- A novel Hopfield network free from the local-minimun difficulty," Analog Integrated Circuits and Signal Processing, vol. 24, no. 1, pp. 51-57 (2000).
  75. Yamada T. and Amemiya Y., "Multiple-valued logic devices using single-electron circuits," Superlattices and Microstructures, vol. 27, no. 5/6, pp. 607-611 (2000).
  76. Sunayama T., Ikebe M., Asai T., and Amemiya Y., "Cellular νMOS circuits performing edge detection with difference-of-Gaussian Filters," Japanese Journal of Applied Physics, vol. 39, no. 4B, pp. 2278-2286 (2000).
  77. Wu N.-J., Lee H., Amemiya Y., and Yasunaga H., "Analog computation using coupled-quantum-dot spin glass," IEICE Transactions on Electronics, vol. E82-C, no. 9, pp. 1623-1629 (1999).
  78. Yamada T. and Amemiya Y., "A multiple-valued Hopfield network device using single-electron circuits," IEICE Transactions on Electronics, vol. E82-C, no. 9, pp. 1615-1622 (1999).
  79. Akazawa M., Kanaami K., Yamada T., and Amemiya Y., "Multiple-valued inverter using a single-electron-tunneling circuit," IEICE Transactions on Electronics, vol. E82-C, no. 9, pp. 1607-1614 (1999).
  80. Morie T., Uchimura K., and Amemiya Y., "Analog LSI implementation of self-learning neural networks," Computers and Electrical Engineering, vol. 25, no. 5, pp. 339-355 (1999).
  81. Tabe M., Terao Y., Nuryadi R., Ishikawa Y., Asahi N., and Amemiya Y., "Simulation of visible light induced effects in a tunnel junction array for photonic device applications," Japanese Journal of Applied Physics, vol. 38, no. 1B, pp. 593-596 (1999).
  82. Wu N.-J., Lee H., Amemiya Y., and Yasunaga H., "Method for determining weight coefficients for quantum Boltzmann machines,"," Japanese Journal of Applied Physics, vol. 38, no. 1B, pp. 439-442 (1999).
  83. Wu N.-J., Shibata N., and Amemiya Y., "Boltzmann machine neuron device using quantum-coupled single electrons," Applied Physics Letters, vol. 72, no. 24, pp. 3214-3216 (1998).
  84. Wu N.-J., Shibata N., and Amemiya Y., "Quantum cellular automaton device using the image charge effect," Japanese Journal of Applied Physics, vol. 37, no. 5A, pp. 2433-2438 (1998).
  85. Iwamura H., Akazawa M., and Amemiya Y., "Single-electron majority logic circuits," IEICE Transactions on Electronics, vol. E81-C, no. 1, pp. 42-48 (1998).
  86. Tabe M., Terao Y., Asahi N., and Amemiya Y., "Photoradiation effects in a single-electron tunnel junction array," IEICE Transactions on Electronics, vol. E81-C, no. 1, pp. 36-41 (1998).
  87. Asahi N., Akazawa M., and Amemiya Y., "Single-electron logic systems based on the binary decision diagram," IEICE Transactions on Electronics, vol. E81-C, no. 1, pp. 49-56 (1998).
  88. Ikebe M., Akazawa M., and Amemiya Y., "A Functional nMOS circuit for implementing cellular-automaton picture-processing devices," Computers and Electrical Engineering, vol. 23, no. 6, pp. 439-451 (1997).
  89. Akazawa M., Shibata N., and Amemiya Y., "Annealing method for operating quantum-cellular-automaton systems," Journal of Applied Physics, vol. 82, no. 10, pp. 5176-5184 (1997).
  90. Akazawa M. and Amemiya Y., "Eliciting the potential functions of single-electron circuits," IEICE Transactions on Electronics, vol. E80-C, no. 7, pp. 849-858 (1997).
  91. Asahi N., Akazawa M., and Amemiya Y., "Single-electron logic device based on the binary decision diagram," IEEE Transactions on Electron Devices, vol. 44, no. 7, pp. 1109-1116 (1997).
  92. Tabe M., Asahi N., Amemiya Y., and Terao Y., "Simulation of relaxation processes for non-equilibrium electron distribution in two-dimensional tunnel junction arrays," Japanese Journal of Applied Physics, vol. 36, no. 6B, pp. 4176-4180 (1997).
  93. Wu N.-J., Asahi N., and Amemiya Y., "Cellular-automaton circuits using single-electron-tunneling junctions," Japanese Journal of Applied Physics, vol. 36, no. 5A, pp. 2621-2627 (1997).
  94. Akazawa M. and Amemiya Y., "Boltzmann machine neuron circuit using single-electron tunneling," Applied Physics Letters, vol. 70, no. 5, pp. 670-672 (1997).
  95. Amemiya Y., "Analog computation using quantum structures - a promising computation architecture for quantum processors -," IEICE Transactions on Electronics, vol. E79-C, no. 11, pp. 1481-1486 (1996).
  96. Akazawa M. and Amemiya Y., "Directional single-electron-tunneling junction," Japanese Journal of Applied Physics, vol. 35, no. 6A, pp. 3569-3575 (1996).
  97. Asahi N., Akazawa M., and Amemiya Y., "Binary-decision-diagram device," IEEE Transactions on Electron Devices, vol. 42, no. 11, pp. 1999-2003 (1995).
  98. Wu N.-J., Hashizume T., Hasegawa H., and Amemiya Y., "Schottky contacts on n-InP with high barrier heights and reduced Fermi-level pinning by a novel in situ electrochemical process," Japanese Journal of Applied Physics, vol. 34, no. 2B, pp. 1162-1167 (1995).
  99. Morie T. and Amemiya Y., "An all-analog expandable neural network LSI with on-chip backpropagation learning," IEEE Journal of Solid-State Circuits, vol. 29, no. 9, pp. 1086-1093 (1994).
  100. Amemiya Y., "Information processing using intelligent materials - information-processing architectures for material processors," Journal of Intelligent Materials Systems and Structures, vol. 5, no. 3, pp. 418-423 (1994).
  101. Aisawa S., Noguchi K., Koga M., Matsumoto T., Amemiya Y., and Sugita A., "Neural-processing-type optical WDM demultiplexer," IEEE Journal of Lightwave Technology, vol. 11, no. 12, pp. 2130-2139 (1993).
  102. Fujita O. and Amemiya Y., "A floating-gate analog memory device for neural networks," IEEE Transactions on Electron Devices, vol. 40, no. 11, pp. 2029-2035 (1993).
  103. Morie T. and Amemiya Y., "Deterministic Boltzmann machine learning improved for analog LSI Implementation," IEICE Transactions on Electronics, vol. E76-C, no. 7, pp. 1167-1173 (1993).

書籍／チャプター

  1. Kikombo A.K., Asai T., and Amemiya Y., "Exploiting temporal noises and device fluctuations in enhancing fidelity of pulse-density modulator consisting of single-electron neural circuits," Neural Information Processing, Leung C.-S., Lee M., and Chan J.H., Eds., Lecture Notes in Computer Science, vol. 5864, pp. 384-391, Springer Berlin / Heidelberg (2009).
  2. Tovar G.M., Asai T., and Amemiya Y., "Noise-tolerant analog circuits for sensory segmentation based on symmetric STDP learning," Advances in Neuro-Information Processing, Koppen M., Kasabov N., and Coghill G, Eds., Lecture Notes in Computer Science, vol. 5507, pp. 851-858, Springer, Berlin / Heidelberg (2009).
  3. Tovar G.M., Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "Analog CMOS circuits implementing neural segmentation model based on symmetric STDP learning," Neural Information Processing, Ishikawa M., Doya K., Miyamoto H., and Yamakawa T., Eds., Lecture Notes in Computer Science, vol. 4985, pp. 117-126, Springer, Berlin / Heidelberg (2008).
  4. Utagawa A., Asai T., Hirose T., and Amemiya Y., "Noise shaping pulse-density modulation in inhibitory neural networks with subthreshold neuron circuits," Brain-Inspired IT III, Natsume K., Hanazawa A., and Miki T., Eds, International Congress Series, vol. 1301, pp. 71-74, Elsevier, Netherlands (2007).
  5. Yamada K., Asai T., Motoike I.N., and Amemiya Y., "On digital VLSI circuits exploiting collision-based fusion gates," From Utopian to Genuine Unconventional Computers, Teuscher C. and Adamatzky A., Eds., pp. 1-16, Luniver Press, U.K. (2006).
  6. Hirose T., Ueno K., Asai T., and Amemiya Y., "Single-flux-quantum circuits for spiking neuron devices," Brain-Inspired IT II, Ishii K., Natsume K., and Hanazawa A., Eds., International Congress Series, vol. 1291, pp. 221-224, Elsevier, Netherlands (2006).
  7. Oya T., Asai T., Kagaya R., Kasai S., and Amemiya Y., "Stochastic resonance among single-electron neurons on Schottky wrap-gate devices," Brain-Inspired IT II, Ishii K., Natsume K., and Hanazawa A., Eds., International Congress Series, vol. 1291, pp. 213-216, Elsevier, Netherlands (2006).
  8. Morie T. and Amemiya Y., "Single-electron functional devices and circuits," Handbook of Theoretical and Computational Nanotechnology, Rieth M. and Schommers W., Eds, vol. 10, chapter 4, pp. 239-318, American Scientific Publishers, Stevenson Ranch, CA (2006).
  9. Oya T., Asai T., and Amemiya Y., "A single-electron reaction-diffusion device for computation of a Voronoi diagram," Unconventional Computing 2005: From Cellular Automata to Wetware, Teuscher C. and Adamatzky A., Eds., pp. 13-26, Luniver Press, U.K. (2005).
  10. Ikebe M. and Amemiya Y., "νMOS cellular-automaton circuit for picture processing," Brainware: Bio-Inspired Architecture and its Hardware Implementation, Miki T., Ed., Chapter 6, pp. 123-162, World Scientific, Singapole (2000).
  11. Amemiya Y., "Circuit systems using quantum-effect devices," Mesoscopic Physics and Electronics, Ando T., Arakawa Y., Furuya K., Komiyama S., and Nakashima H., Eds., Chapter 5.1, pp. 220-226, Springer (1997).

特許

  1. Hirose T., Asai T., Amemiya Y., and Ueno K., "Reference voltage generation circuit," 国際公開番号 WO 2009/014042, 国際公開日 2009年1月29日.

招待講演／セミナー

  1. Ali E.J., Amemiya Y., Hagiwara N., Akai-Kasaya M., and Asai T., "A comparison between simulations and experiments of neuromorphic devices using electropolymerization of conductive polymer nanowires," Joint Symposium of JSPS-DST Bilateral Research on Charge- and Spin-Blockade in Ultrathin-Layers of Single Molecule Magnets, online, Japan (Feb. 24, 2021).
  2. Asai T. and Amemiya Y., "Silicon implementation of reaction-diffusion cellular automata for computational geometry," Satellite Session on Quantum Nano Electronics for Meme-Media-Based Information Technologies; the 7th Hokkaido University - Seoul National University Joint Symposium, Sapporo, Japan (Jul. 8-9, 2004).
  3. Asai T. and Amemiya Y., "Biomorphic analog circuits based on reaction-diffusion systems," Proceedings of the 33rd International Symposium on Multiple-Valued Logic, pp. 197-204, Meiji University, Tokyo, Japan (May 16-19, 2003).
  4. Asai T. and Amemiya Y., "Reaction-diffusion systems on excitable semiconductor medium," Collected Abstracts of 2003 RCIQE International Seminar on Quantum Nanoelectronics for Meme-Media-Based Information Technologies, pp. 64-71, Hokkaido University, Sapporo, Japan (Feb. 12-14, 2003).
  5. Asai T. and Amemiya Y., "Natural computation with analog reaction-diffusion circuits," Proceedings of the 2002 International Symposium on New Paradigm VLSI Computing, pp. 117-120, Tohoku University, Sendai, Japan (Dec. 12-14, 2002).
  6. Asai T., Hayasi H., and Amemiya Y., "Analog integrate-and-fire neurochips: neural competition in frequency and time domains," World Automation Congress 2002, IFMIP-037, Sheraton World Resort Orlando, Florida, U.S.A. (Jun. 9-13, 2002).

国際会議

  1. Hagiwara N., Amemiya Y., Ali E.J., Asai T., and Akai-Kasaya M., "Feasibility of neuromorphic wetware using configurable polymer networks," The 10th RIEC International Symposium on Brain Functions and Brain Computer, Online, (Feb. 18-19, 2022).
  2. Amemiya Y., Ali E.J., Hagiwara N., Akai-Kasaya M., and Asai T., "A heuristic model for configurable polymer-wire synaptic devices," The 2021 Nonlinear Science Workshop, Online (Dec. 6-8, 2021).
  3. Ali E.J., Amemiya Y., Akai-Kasaya M., and Asai T., "Smart hardware architecture with random weight elimination and weight balancing algorithms," The 2021 Nonlinear Science Workshop, Online (Dec. 6-8, 2021).
  4. Amemiya Y., Ali E.J., Akai-Kasaya M., and Asai T., "A cellular automata model for unstructured, flexible, and configurable molecular synapses toward edge-AI computing," 2020 International Symposium on Nonlinear Theory and Its Applications, Online, Japan (Nov. 16-19, 2020).
  5. Tovar G.M., Asai T., and Amemiya Y., "Array-enhanced stochastic resonance in a network of noisy neuromorhic circuits," Proceedings of the 17th International Conference on Neural Information Processing, pp. 188-196, Sydney, Australia (Nov. 22-25, 2010).
  6. Akoh N., Asai T., Yanagida T., Kawai T., and Amemiya Y., "A ReRAM-based analog synaptic device having spike-timing-dependent plasticity," Nanoelectronics Days 2010, p. 19, Aachen, Germany (Oct. 4-7, 2010).
  7. Shimada H., Ueno K., Asai T., and Amemiya Y., "On-chip power supply for subthreshold-operated CMOS LSIs," Proceedings of the 9th International Conference on System Science and Simulation in Engineering, pp. 198-200, Iwate, Japan (Oct. 4-6, 2010).
  8. Ueno K., Shimada H., Asai T., and Amemiya Y., "Low-voltage power supply regulator for subthreshold-operated CMOS digital LSIs," 2010 International Conference on Solid State Devices and Materials, Tokyo, Japan (Sep. 22-24, 2010).
  9. Akoh N., Asai T., Amemiya Y., Yanagida T., and Kawai T., "A behavioral model of unipolar resistive RAMs and its application to HSPICE integration," The 17th International Workshop on Oxide Electronics, #167, Hyogo, Japan (Sep. 19-22, 2010).
  10. Utagawa A., Asai T., and Amemiya Y., "Stochastic resonance in a simple electric circuit having a double-well potential ---Circuit experiments with a single operational amplifier---," Proceedings of 2010 International Symposium on Nonlinear Theory and its Applications, pp. 55-59, Krakow, Poland (Sep. 5-8, 2010).
  11. Iida T., Asai T., Amemiya Y., and Sano E., "An offset compensation method using subthreshold CMOS operational amplifiers for fully differential amplifiers," Integrated Circuits and Devices in Vietnam 2010, Ho Chi Minh, Vietnam (Aug. 16, 2010).
  12. Utagawa A., Asai T., and Amemiya Y., "Stochastic resonance in neuromorphic semiconductor devices having a double-well potential," Proceedings of the 14th International Conference on Cognitive and Neural Systems, p. 86, Boston, U.S.A. (May 19-22, 2010).
  13. Tovar G.M., Asai T., and Amemiya Y., "Coupling-enhanced stochastic resonance in noisy neuromorphic devices," Proceedings of the 14th International Conference on Cognitive and Neural Systems, p. 87, Boston, U.S.A. (May 19-22, 2010).
  14. Akoh N., Asai T., and Amemiya Y., "Towards memristor-CMOS-hybrid semiconductor devices for neural networks," Proceedings of the 14th International Conference on Cognitive and Neural Systems, p. 85, Boston, U.S.A. (May 19-22, 2010).
  15. Ueno K., Asai T., and Amemiya Y., "Ultra-low power LSIs consisting of subthreshold CMOS circuits --Micropower circuit components for power-aware LSI applications--," Proceedings of the 3rd International Symposium on Global COE Program of Center for Next-Generation Information Technology Based on Knowledge Discovery and Knowledge Federation, pp. 259-260, Sapporo, Japan (Jan. 18-20, 2010).
  16. Kikombo A.K., Asai T., and Amemiya Y., "Single-electron pulse-density modulation circuits employing device fabrication mismatches and temporal noises to achieve high signal to noise ratio," Proceedings of the 3rd International Symposium on Global COE Program of Center for Next-Generation Information Technology Based on Knowledge Discovery and Knowledge Federation, p. xvii, Sapporo, Japan (Jan. 18-20, 2010).
  17. Kikombo A.K., Asai T., and Amemiya Y., "Morphic circuit architectures for beyond CMOS LSIs using failure-prone nano-electronic devices," Proceedings of the 3rd International Symposium on Global COE Program of Center for Next-Generation Information Technology Based on Knowledge Discovery and Knowledge Federation, pp. 254-256, Sapporo, Japan (Jan. 18-20, 2010).
  18. Utagawa A., Asai T., and Amemiya Y., "Neural network circuit exhibiting high-fidelity pulse-density modulation based on a model of vestibulo-ocular reflex," Proceedings of the 3rd International Symposium on Global COE Program of Center for Next-Generation Information Technology Based on Knowledge Discovery and Knowledge Federation, pp. 232-233, Sapporo, Japan (Jan. 18-20, 2010).
  19. Iida T., Asai T., Sano E., and Amemiya Y., "Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers," Proceedings of the 16th IEEE International Conference on Electronics, Circuits, and Systems, pp. 140-143, Hammamet, Tunisia (Dec. 13-16, 2009).
  20. Kikombo A.K., Asai T., and Amemiya Y., "Bio-inspired single-electron circuit architectures exploiting thermal noises and device fluctuations to enhance signal transmission fidelity," Proceedings of the 2009 International Symposium on Intelligent Signal Processing and Communication Systems, pp. 429-432, Kanazawa, Japan (Dec. 7-9, 2009).
  21. Utagawa A., Asai T., and Amemiya Y., "Noise-driven image processing based on array-enhanced stochastic resonance with population heterogeneity," Proceedings of the 2009 International Symposium on Intelligent Signal Processing and Communication Systems, pp. 437-440, Kanazawa, Japan (Dec. 7-9, 2009).
  22. Kikombo A.K., Asai T., and Amemiya Y., "Exploiting temporal noises and device fluctuations in enhancing fidelity of pulse-density modulator consisting of single-electron neural circuits," Proceedings of the 16th International Conference on Neural Information Processing, pp. 384-391, Bangkok, Thailand (Dec. 1-5, 2009).
  23. Ueno K., Asai T., and Amemiya Y., "A 0.02-to-2-MHz tunable clock reference circuit for intermittent pulse generators," Proceedings of the 2009 IEEJ International Analog VLSI Workshop, pp. 5-10, Chiangmai, Thailand (Nov. 18-20, 2009).
  24. Utagawa A., Asai T., and Amemiya Y., "A noise-driven neuromorphic pulse-density modulator: experimental results with discrete MOS devices," Proceedings of the 2009 International Symposium on Nonlinear Theory and its Applications, pp. 206-209, Sapporo, Japan (Oct. 18-21, 2009).
  25. Kikombo A.K., Asai T., and Amemiya Y., "Pulse-density modulation with an ensemble of single-electron circuits employing neuronal heterogeneity to achieve high temporal resolution," Proceedings of the 4th International Conference on Nano-Networks, pp. 51-56, Luzern, Switzerland (Oct. 18-20, 2009).
  26. Ueno K., Asai T., and Amemiya Y., "A 30-MHz 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop," Proceedings of the 35th European Solid-State Circuits Conference, pp. 392-395, Athens, Greece (Sep. 14-18, 2009).
  27. Kikombo A.K., Asai T., and Amemiya Y., "Noise-driven architectures toward beyond CMOS LSIs with failure-prone nano-electronic devices," Proceedings of the 14th International Commercialization of Micro and Nano Systems Conference, p. 18, Copenhagen, Denmark (Aug. 30-Sep. 4, 2009).
  28. Ueno K., Asai T., and Amemiya Y., "A PTAT voltage source consisting of subthreshold MOSFETs for temperature sensor LSIs," Proceedings of the 24th International Technical Conference on Circuits/Systems, Computers and Communications, pp. 225-226, Jeju Island, Korea (Jul. 5-8, 2009).
  29. Iida T., Asai T., Sano E., and Amemiya Y., "Level-shift circuit using subthreshold-operated CMOS operational amplifiers," Proceedings of the 24th International Technical Conference on Circuits/Systems, Computers and Communications, pp. 209-212, Jeju Island, Korea (Jul. 5-8, 2009).
  30. Asai S., Ueno K., Asai T., and Amemiya Y., "High-resistance resistors consisting of subthreshold-operated CMOS circuits ---LSI implementation of 1-1000 mega ohm resistors----," Proceedings of the 24th International Technical Conference on Circuits/Systems, Computers and Communications, pp. 221-224, Jeju Island, Korea (Jul. 5-8, 2009).
  31. Ueno K., Asai T., and Amemiya Y., "Temperature-to-frequency converter consisting of subthreshold MOSFET circuits for smart temperature-sensor LSIs," Proceedings of the 15th International Conference on Solid-State Sensors, Actuators and Microsystems, pp. 2433-2436, Denver, U.S.A. (Jun. 21-25, 2009).
  32. Utagawa A., Asai T., and Amemiya Y., "Noise-induced phase synchronization among analogue oscillator circuits: Experimental results with discrete MOS devices," Proceedings of the 17th International Workshop on Nonlinear Dynamics of Electronic Systems, pp. 110-113, Rapperswil, Switzerland (Jun. 21-24, 2009).
  33. Kikombo A.K., Asai T., Oya T., Schmid A., Leblebici Y., and Amemiya Y., "A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons," Proceedings of the 2009 International Joint Conference on Neural Networks, pp. 1600-1605, Atlanta, U.S.A. (Jun. 14-19, 2009).
  34. Utagawa A., Asai T., and Amemiya Y., "High-fidelity neuromorphic pulse-sendity modulator based on a model of vestibulo-ocular reflex," Proceedings of the 13th International Conference on Cognitive and Neural Systems, p. 140, Boston, U.S.A. (May 27-30, 2009).
  35. Ueno K., Asai T., and Amemiya Y., "Low-power clock reference circuit for intermittent operation of subthreshold LSIs," Proceedings of the 2009 International Symposium on Circuits and Systems, pp. 5-8, Taipei, Taiwan (May 24-27, 2009).
  36. Tsugita Y., Ueno K., Hirose T., Asai T., and Amemiya Y., "On-chip PVT compensation techniques for low-voltage CMOS digital LSIs," Proceedings of the 2009 International Symposium on Circuits and Systems, pp. 1565-1568, Taipei, Taiwan (May 24-27, 2009).
  37. Utagawa A., Asai T., and Amemiya Y., "High-fidelity pulse-density modulation with noisy neuromorphic circuits based on a model of vestibulo-ocular reflex," Proceedings of the 2009 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 293-296, Honolulu, U.S.A. (Mar. 1-3, 2009).
  38. Sahashi T., Utagawa A., Asai T., and Amemiya Y., "Theoretical analysis of collective stochastic resonance with population heterogeneity," Proceedings of the 2009 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 605-608, Honolulu, U.S.A. (Mar. 1-3, 2009).
  39. Fujita D., Asai T., and Amemiya Y., "A CMOS frequency comparator based on jamming avoidance response of Eigenmannia," Proceedings of the 2009 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 653-656, Honolulu, U.S.A. (Mar. 1-3, 2009).
  40. Yamada K., Asai T., and Amemiya Y., "Towards compact low-power digital circuits exploiting collision-based fusion gates," Proceedings of the 2009 International Symposium on Multimedia and Communication Technology, pp. 245-249, Bangkok, Thailand (Jan. 22-23, 2009).
  41. Ueno K., Asai T., and Amemiya Y., "An ultra-low power clock reference generator for subthreshold LSIs," Proceedings of the 2009 International Symposium on Multimedia and Communication Technology, pp. 230-234, Bangkok, Thailand (Jan. 22-23, 2009).
  42. Ueno K., Hirose T., Asai T., and Amemiya Y., "An ultra-low power CMOS voltage reference circuit based on subthreshold MOSFETs for on-chip process compensation in analog circuits," Proceedings of the 2nd International Symposium on Global COE Program of Center for Next-Generation Information Technology Based on Knowledge Discovery and Knowledge Federation, pp. 249-250, Sapporo, Japan (Jan. 20-21, 2009).
  43. Kikombo A.K., Asai T., and Amemiya Y., "Fault-tolerant architectures for single-electronic circuits based on neural networks," Proceedings of the 2nd International Symposium on Global COE Program of Center for Next-Generation Information Technology Based on Knowledge Discovery and Knowledge Federation, pp. 275-276, Sapporo, Japan (Jan. 20-21, 2009).
  44. Yamada K., Asai T., and Amemiya Y., "Logical system for single-flux quantum circuits with asynchronous collision-based fusion gates," Proceedings of the 2nd International Symposium on Global COE Program of Center for Next-Generation Information Technology Based on Knowledge Discovery and Knowledge Federation, pp. 287-289, Sapporo, Japan (Jan. 20-21, 2009).
  45. Ueno K., Hirose T., Asai T., and Amemiya Y., "A 300 nW, 7 ppm/°C CMOS voltage reference circuit based on subthreshold MOSFETs," Proceedings of the 14th Asia and South Pacific Design Automation Conference, pp. 95-96, Yokohama, Japan (Jan. 19-22, 2009).
  46. Kikombo A.K., Schmid A., Asai T., Leblebici Y., and Amemiya Y., "Fault-tolerant architectures for nanoelectronic circuits employing simple feed-forward neural networks without learning," Proceedings of the 15th International Conference on Neural Information Processing of the Asia-Pacific Neural Network Assembly, p. 328, Auckland, New Zealand (Nov. 25-28, 2008).
  47. Tovar G.M., Asai T., and Amemiya Y., "Noise-tolerant analog circuits for sensory segmentation based on symmetric STDP learning," Proceedings of the 15th International Conference on Neural Information Processing of the Asia-Pacific Neural Network Assembly, pp. 199-200, Auckland, New Zealand (Nov. 25-28, 2008).
  48. Ueno K., Hirose T., Asai T., and Amemiya Y., "A 46-ppm/°C temperature and process compensated current reference with on-chip threshold voltage monitoring circuit," Proceedings of the IEEE Asian Solid-State Circuits Conference 2008, pp. 161-164, Fukuoka, Japan (Nov. 3-5, 2008).
  49. Yamada K., Asai T., and Amemiya Y., "Single-flux-quantum dual-rail logic circuits with asynchronous collision-based fusion gates," The 21st International Symposium on Superconductivity, FDP-26, Tsukuba, Japan (Oct. 27-29, 2008).
  50. Asai T., Utagawa A., and Amemiya Y., "On-chip CMOS clock generators exhibiting noise-induced synchronous oscillation," Proceedings of the 9th Japan-Korea Joint Workshop on Advanced Semiconductor Processes and Equipments, pp. 150-159, Hakodate, Japan (Oct. 9-11, 2008).
  51. Ueno K., Asai T., and Amemiya Y., "Current reference circuit for subthreshold CMOS LSIs," Extended Abstract of the 2008 International Conference on Solid State Devices and Materials, pp. 1000-1001, Ibaraki, Japan (Sep. 23-26, 2008).
  52. Yamada K., Asai T., and Amemiya Y., "Single-flux quantum circuits for digital cellular automata and analog reaction-diffusion computing," Proceedings of the 3rd International Workshop on Natural Computing, p. 85, Yokohama, Japan (Sep. 23, 2008).
  53. Ueno K., Hirose T., Asai T., and Amemiya Y., "A 0.3-µW, 7 ppm/°C CMOS voltage reference circuit for on-chip process monitoring in analog circuits," Proceedings of the 34th European Solid-State Circuits Conference, pp. 398-401, Edinburgh, U.K. (Sep. 15-19, 2008).
  54. Utagawa A., Asai T., Sahashi T., and Amemiya Y., "Stochastic resonance in retinomorphic neural networks with nonidentical photoreceptors and noisy McCulloch-Pitts neurons," Proceedings of the 2008 International Symposium on Nonlinear Theory and its Applications, pp. 124-127, Budapest, Republic of Hungary (Sep. 7-10, 2008).
  55. Kawabata K., Asai T., and Amemiya Y., "Circuit implementation of historic analog cellular automata based on Wolfram's Rule 90 and 150," Proceedings of the 16th International Workshop on Nonlinear Dynamics of Electronic Systems, pp. 30-31, Nizhny Novgorod, Russia (Jul. 20-26, 2008).
  56. Hirai T., Asai T., and Amemiya Y., "CMOS phase-shift oscillator using the conduction of heat," Proceedings of the 2008 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, pp. 249-252, Sapporo, Japan (Jul. 9-11, 2008).
  57. Kikombo A.K., Asai T., and Amemiya Y., "An insect vision-based single-electron circuit performing motion detection," Proceedings of the 2008 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, pp. 159-164, Sapporo, Japan (Jul. 9-11, 2008).
  58. Ogawa T., Hirose T., Asai T., and Amemiya Y., "Low voltage operation of master-slave flip-flops for ultra-low power subthreshold LSIs," The International Conference on Electrical Engineering 2008, O-166, Okinawa, Japan (Jul. 6-10, 2008).
  59. Yamada K., Asai T., and Amemiya Y., "Combinational logic computing for single-flux quantum circuits with asynchronous collision-based fusion gates," The 23rd International Technical Conference on Circuits/Systems, Computers and Communications, Shimonoseki, Japan (Jul. 6-9, 2008).
  60. Kikombo A.K., Asai T., and Amemiya Y., "A neuromorphic circuit for motion detection with single-electron devices based on correlation neural networks," The 2008 IEEE Silicon Nanoelectronics Workshop, #P1-31, Honolulu, U.S.A. (Jun. 15-16, 2008).
  61. Kikombo A.K., Schmid A., Asai T., Leblebici Y., and Amemiya Y., "Implementation of early vision model for edge extraction with single-slsecton devices," Proceedings of the 12th International Conference on Cognitive and Neural Systems, p. 125, Boston, U.S.A. (May 14-17, 2008).
  62. Kikombo A.K., Asai T., and Amemiya Y., "Morphic approaches toward establishing emerging image processing architectures for Beyond CMOS nano-electronic devices," The 4th International Nanotechnology Conference on Communications and Cooperation, Japan Session Poster #1, Tokyo, Japan (Apr. 14-17, 2008).
  63. Kikombo A.K., Schmid A., Asai T., Leblebici Y., and Amemiya Y., "Toward a single-electron image processor for edge detection based on the inner retina model," Proceedings of the 2008 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 267-270, Gold Coast, Australia (Mar. 6-8, 2008).
  64. Utagawa A., Asai T., Hirose T., and Amemiya Y., "Noise-induced phase synchronization between nonidentical analog CMOS osscillators," Proceedings of the 2008 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 160-163, Gold Coast, Australia (Mar. 6-8, 2008).
  65. Tovar G.M., Fujita D., Asai T., Hirose T., and Amemiya Y., "Neuromorphic MOS circuits implementing a temporal coding neural model," Proceedings of the 2008 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 371-374, Gold Coast, Australia (Mar. 6-8, 2008).
  66. Kikombo A.K., Asai T., Hirose T., and Amemiya Y., "Neuromorphic nano-electronic circuits performing edge enhancement with single-electron devices," Proceedings of the 2008 International Symposium on Global COE Program of Center for Next-Generation Information Technology based on Knowledge Discovery and Knowledge Federation, pp. 137-138, Sapporo, Japan (Jan. 22-23, 2008).
  67. Kikombo A.K., Schmid A., Leblebici Y., Asai T., and Amemiya Y., "A bio-inspired image processor for edge detection with single-electron circuits," 2007 International Semiconductor Device Research Symposium, #TA3-04, Maryland, U.S.A. (Dec. 12-14, 2007).
  68. Tovar G.M., Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "Analog CMOS circuits implementing neural segmentation model based on symmetric STDP learning," Proceedings of the 14th International Conference on Neural Information Processing, pp. 306-315, Kitakyushu, Japan (Nov. 13-16, 2007).
  69. Ogawa T., Hirose T., Asai T., and Amemiya Y., "Threshold-logic systems consisting of subthreshold CMOS circuits," Proceedings of the 2007 IEEJ International Analog VLSI Workshop, pp. 78-83, Limerick, Ireland (Nov. 7-9, 2007).
  70. Asai T. and Amemiya Y., "Single-flux quantum logic circuits exploiting collision-based fusion gates," Proceedings of the 20th International Symposium on Superconductivity, p. 327, Tsukuba, Japan (Nov. 5-7, 2007).
  71. Ueno K., Hirose T., Asai T., and Amemiya Y., "CMOS voltage reference based on the threshold voltage of a MOSFET," Extended abstract of the 2007 International Conference on Solid State Devices and Materials, pp. 486-487, Ibaraki, Japan (Sep. 18-21, 2007).
  72. Kikombo A.K., Tabe M., and Amemiya Y., "Photon position detector consisting of single-electron devices," Extended Abstract of the 2007 International Conference on Solid State Devices and Materials, pp. 1114-1115, Ibaraki, Japan (Sep. 18-21, 2007).
  73. Utagawa A., Asai T., Hirose T., and Amemiya Y., "Noise-induced synchronization among sub-RF CMOS neural oscillators for skew-free clock distribution," Proceedings of the 2007 International Symposium on Nonlinear Theory and its Applications, pp. 329-332, Vancouver, Canada (Sep. 16-19, 2007).
  74. Tovar G.M., Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "Neuromorphic CMOS circuits implementing a novel neural segmentation model based on symmetric STDP learning," Proceedings of the 2007 International Joint Conference on Neural Networks, pp. 897-901, Florida, U.S.A. (Aug. 12-17, 2007).
  75. Joye N., Schmid A., Leblebici Y., Asai T., and Amemiya Y., "Fault-tolerant logic gates using neuromorphic CMOS circuits," The 3rd Conference on Ph.D. Research in Microelectronics and Electronics, DIGITAL IC-5, Bordeaux, France (Jul. 2-5, 2007).
  76. Kikombo A.K., Hirose T., Asai T., and Amemiya Y., "Multi-valued logic circuits consisting of single-electron devices," Proceedings of the 2007 Silicon Nanoelectronics Workshop, pp. 81-82, Kyoto, Japan (Jun. 10-11, 2007).
  77. Ueno K., Hirose T., Asai T., and Amemiya Y., "Floating millivolt reference for PTAT current generation in subthreshold MOS LSIs," Proceedings of the 2007 IEEE International Symposium on Circuits and Systems, pp. 3748-3751, New Orleans, U.S.A. (May 27-30, 2007).
  78. Asai T., Oya T., and Amemiya Y., "Single-electron circuits performing noise-tolerant pulse-density modulation based on neuromorphic architecture," Abstract of the Nanotech Northern Europe 2007, p. 79, Helsinki, Finland (Mar. 27-29, 2007).
  79. Ueno K., Hirose T., Asai T., and Amemiya Y., "Ultralow-power smart temperature sensor consisting of subthreshold MOS circuits," Collected Papers of the 4th International Symposium on Ubiquitous Knowledge Network Environment, p. 73, Sapporo, Japan (Mar. 5-7, 2007).
  80. Kikombo A.K., Hirose T., Asai T., and Amemiya Y., "Non-linear dynamics of coupled single-electron oscillator systems," Collected Papers of the 4th International Symposium on Ubiquitous Knowledge Network Environment, p. 72, Sapporo, Japan (Mar. 5-7, 2007).
  81. Yamada K., Asai T., Hirose T., and Amemiya Y., "Scale reduction of logic circuits for low-power digital LSIs with collision-based fusion gate ," Collected Papers of the 4th International Symposium on Ubiquitous Knowledge Network Environment, p. 71, Sapporo, Japan (Mar. 5-7, 2007).
  82. Asai T. and Amemiya Y., "Reaction-diffusion computers," Collected Papers of the 4th International Symposium on Ubiquitous Knowledge Network Environment, pp. 75-89, Sapporo, Japan (Mar. 5-7, 2007).
  83. Utagawa A., Asai T., Hirose T., and Amemiya Y., "An inhibitory neural network circuit exhibiting noise shaping with subthreshold MOS neuron circuits," Proceedings of the 2007 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 165-168, Shanghai, China (Mar. 3-6, 2007).
  84. Tovar G.M., Asai T., Hirose T., and Amemiya Y., "Critical temperature sensor based on spiking neuron models: experimental results with discrete MOS circuits," Proceedings of the 2007 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 599-602, Shanghai, China (Mar. 3-6, 2007).
  85. Fukuda E.S., Asai T., Hirose T., and Amemiya Y., "A novel segmentation model for neuromorphic CMOS circuits," Proceedings of the 2007 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 489-492, Shanghai, China (Mar. 3-6, 2007).
  86. Hirose T., Asai T., and Amemiya Y., "Power supply circuits for ultralow-power subthreshold CMOS smart sensor LSIs," Proceedings of the 2006 International Symposium on Intelligent Signal Processing and Communication Systems, pp. 558-561, Tottori, Japan (Dec. 12-15, 2006).
  87. Ueno K., Hirose T., Asai T., and Amemiya Y., "Ultralow-power smart temperature sensor with subthreshold CMOS circuits," Proceedings of the 2006 International Symposium on Intelligent Signal Processing and Communication Systems, pp. 546-549, Tottori, Japan (Dec. 12-15, 2006).
  88. Hagiwara A., Hirose T., Asai T., and Amemiya Y., "Critical temperature switch : a highly sensitive thermosensing device consisting of subthreshold MOSFET circuits," Proceedings of the 2006 International Symposium on Intelligent Signal Processing and Communication Systems, pp. 111-114, Tottori, Japan (Dec. 12-15, 2006).
  89. Hirose T., Asai T., and Amemiya Y., "Pulsed neural networks consisting of single-flux-quantum spiking neurons," Program and Abstracts of the 19th International Symposium on Superconductivity, p. 329, Nagoya, Japan (Oct. 30-Nov. 1, 2006).
  90. Utagawa A., Asai T., Hirose T., and Amemiya Y., "Noise shaping pulse-density modulation in inhibitory neural networks with noise-sensitive subthreshold neuron circuits," Abstracts of the 3rd International Conference of Brain-inspired Information Technology, p. 42, Kitakyushu, Japan (Sep. 27-29, 2006).
  91. Tovar G.M., Hirose T., Asai T., and Amemiya Y., "Critical temperature sensor based on spiking neuron models," Proceedings of the 2006 International Symposium on Nonlinear Theory and its Applications (WIP session), pp. 84-88, Bologna, Italy (Sep. 11-14, 2006).
  92. Yamada K., Asai T., Motoike I.N., and Amemiya Y., "On digital VLSI circuits exploiting collision-based fusion gates," Proceedings of the 5th International Conference on Unconventional Computation, UC 2006, pp. 1-16, York, U.K. (Sep. 4-8, 2006).
  93. Ueno K., Hirose T., Asai T., and Amemiya Y., "A watchdog sensor for assuring the quality of various perishables with subthreshold CMOS circuits," Proceedings of the 2006 Symposia on VLSI Technology and Circuits, pp. 194-195, Honolulu, U.S.A. (Jun. 13-17, 2006).
  94. Kikombo A.K., Hirose T., Asai T., and Amemiya Y., "Non-linear dynamical systems consisting of single-electron oscillators," Proceedings of the 14th International Workshop on Nonlinear Dynamics of Electronic Systems, pp. 81-84, Dijon, France (Jun. 6-9, 2006).
  95. Utagawa A., Asai T., Hirose T., and Amemiya Y., "A neuromorphic LSI performing noise-shaping pulse-density modulation with ultralow-power subthreshold neuron circuits," Proceedings of the 10th International Conference on Cognitive and Neural Systems, p. 53, Boston, U.S.A. (May 17-20, 2006).
  96. Tovar G.M., Hirose T., Asai T., and Amemiya Y., "Precisely-timed synchronization among spiking neural circuits on analog VLSIs," Proceedings of the 2006 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 62-65, Honolulu, U.S.A. (Mar. 3-5, 2006).
  97. Asai T. and Amemiya Y., "Collision-based reaction-diffusion computing for VLSI systems," Proceedings of the 3rd International Symposium on Ubiquitous Knowledge Network Environment, pp. 107-114, Sapporo, Japan (Feb. 28-Mar. 1, 2006).
  98. Oya T., Asai T., and Amemiya Y., "Single-electron reaction-diffusion systems and their application to analog computation," Proceedings of the 3rd International Symposium on Ubiquitous Knowledge Network Environment, p. 45, Sapporo, Japan (Feb. 28-Mar. 1, 2006).
  99. Kikombo A.K., Asai T., and Amemiya Y., "Single-electron discrete dynamical systems," Proceedings of the 3rd International Symposium on Ubiquitous Knowledge Network Environment, p. 47, Sapporo, Japan (Feb. 28-Mar. 1, 2006).
  100. Oya T., Asai T., and Amemiya Y., "Single-electron devices for reaction-diffusion computing," 2006 RCIQE International Seminar for 21st Century COE Program: "Quantum Nanoelectronics for Meme-Media-Based Information Technologies (IV), Sapporo, Japan (Feb. 9-10, 2006).
  101. Hirose T., Matsuoka T., Taniguchi K., Asai T., and Amemiya Y., "Ultralow-power temperature-insensitive current reference circuit," Technical Program and Abstracts of the 4th IEEE Conference on Sensors, p. 186, California, U.S.A. (Oct. 31-Nov. 3, 2005).
  102. Ueno K., Hirose T., Asai T., and Amemiya Y., "A CMOS watch-dog sensor for guaranteeing the quality of perishables," Technical Program and Abstracts of the 4th IEEE Conference on Sensors, p. 186, California, U.S.A. (Oct. 31-Nov. 3, 2005).
  103. Hirose T., Asai T., and Amemiya Y., "Spiking neuron devices consisting of single-flux-quantum circuits," Program and Abstracts of the 18th International Symposium on Superconductivity, p. 327, Tsukuba, Japan (Oct. 24-26, 2005).
  104. Kagaya R., Oya T., Asai T., and Amemiya Y., "Stochastic resonance in an ensemble of single-electron neuromorphic devices and its application to competitive neural networks," Proceedings of the 2005 International Symposium on Nonlinear Theory and its Applications, pp. 329-332, Bruges, Belgium (Oct. 18-21, 2005).
  105. Hirose T., Ueno K., Asai T., and Amemiya Y., "Single-flux-quantum circuits for spiking neuron devices," Proceedings of the 2nd International Conference of Brain-inspired Information Technology, p. 67, Kita-kyushu, Japan (Oct. 7-9, 2005).
  106. Oya T., Asai T., Kagaya R., Kasai S., and Amemiya Y., "Stochastic resonance among single-electron neurons on Schottky wrap-gate devices," Proceedings of the 2nd International Conference of Brain-inspired Information Technology, p. 78, Kita-kyushu, Japan (Oct. 7-9, 2005).
  107. Kikombo A.K., Oya T., Asai T., and Amemiya Y., "Discrete dynamical systems consisting of single-electron circuits," Proceedings of the 13th International IEEE Workshop on Nonlinear Dynamics of Electronic Systems, S13, Potsdam, Germany (Sep. 18-22, 2005).
  108. Oya T., Asai T., and Amemiya Y., "A single-electron reaction-diffusion device for computation of a Voronoi diagram," Proceedings of the VIIIth European Conference on Artificial Life, pp. 23-34, Kent, U.K. (Sep. 5-9, 2005).
  109. Nakada K., Asai T., Hirose T., and Amemiya Y., "Analog current-mode implementation of central pattern generator for robot locomotion," Proceedings of the International Joint Conference on Neural Networks 2005, pp. 639-644, Montreal, Canada (Jul. 31-Aug. 4, 2005).
  110. Oya T., Asai T., Kagaya R., and Amemiya Y., "Noise performance of single-electron depressing synapses for neuronal synchrony detection," Proceedings of the International Joint Conference on Neural Networks 2005, pp. 2849-2854, Montreal, Canada (Jul. 31-Aug. 4, 2005).
  111. Oya T., Asai T., and Amemiya Y., "A single-electron device for computational geometry -- constructing the Voronoi diagram by means of single-electron circuits," Proceedings of the 2005 Silicon Nanoelectronics Workshop, pp. 128-129, Kyoto, Japan (Jun. 12-13, 2005).
  112. Oya T., Schmid A., Asai T., Leblebici Y., and Amemiya Y., "Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2535-2538, Kobe, Japan (May 23-26, 2005).
  113. Nakada K., Asai T., Hirose T., and Amemiya Y., "Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1923-1926, Kobe, Japan (May 23-26, 2005).
  114. Kagaya R., Oya T., Asai T., and Amemiya Y., "Stochastic resonance in an emsemble of single-electron neuromorphic devices," Proceedings of the 9th International Conference on Cognitive and Neural Systems, II-#28, Boston, U.S.A. (May 18-21, 2005).
  115. Oya T., Asai T., Kagaya R., and Amemiya Y., "Single-electron synaptic depression," Proceedings of the 9th International Conference on Cognitive and Neural Systems, II-#27, Boston, U.S.A. (May 18-21, 2005).
  116. Nakada K., Asai T., and Amemiya Y., "Towards development of sensor agents: applications of analog CPG chip," The 2nd International Symposium on Ubiquitous Knowledge Network Environment, Sapporo, Japan (Mar. 16-18, 2005).
  117. Asai T., Motoike I.N., and Amemiya Y., "An analog-digital hybrid reaction-diffusion chip for stripe and spot image restoration," The 2nd International Symposium on Ubiquitous Knowledge Network Environment, Sapporo, Japan (Mar. 16-18, 2005).
  118. Oya T., Asai T., Kagaya R., Hirose T., and Amemiya Y., "Depressing properties of a hardware synapse on a single-layer nanodot array," Proceedings of the 2005 RISP International Workshop on Nonlinear Circuits and Signal Processing, pp. 159-162, Hawaii, U.S.A. (Mar. 4-6, 2005).
  119. Oya T., Asai T., Kagaya R., Hirose T., and Amemiya Y., "Application of the competitive neural-network architecture to single-electron circuit systems," Proceedings of the 2005 RCIQE International Seminar for 21st Century COE Program: Quantum Nanoelectronics for Meme-Media-Based Information Technologies (III), pp. 148-149, Sapporo, Japan (Feb. 8-10, 2005).
  120. Nakada K., Asai T., and Amemiya Y., "Analog current-mode implementation of neuromorphic oscillator for robot locomotion," Proceedings of the 2005 RCIQE International Seminar for 21st Century COE Program: Quantum Nanoelectronics for Meme-Media-Based Information Technologies (III), pp. 150-151, Sapporo, Japan (Feb. 8-10, 2005).
  121. Nakada K., Asai T., and Amemiya Y., "Analog CMOS implementation of a bursting oscillator with depressing synapse," Proceedings of the International Conference on Intelligent Sensors, Sensor Networks and Information Processing, pp. 503-506, Melbourne, Australia (Dec. 14-17, 2004).
  122. Oya T., Asai T., Kagaya R., Hirose T., and Amemiya Y., "Neuromorphic single-electron circuit and its application to temporal-domain neural competition," Proceedings of the 2004 International Symposium on Nonlinear Theory and its Application, pp. 235-239, Fukuoka, Japan (Nov. 29-Dec. 3, 2004).
  123. Takahashi M., Oya T., Hirose T., Asai T., and Amemiya Y., "A CMOS reaction-diffusion device using minority-carrier diffusion in seminonductors," Proceedings of the 2004 International Symposium on Nonlinear Theory and its Application, pp. 601-605, Fukuoka, Japan (Nov. 29-Dec. 3, 2004).
  124. Nakada K., Asai T., Hirose T., and Amemiya Y., "Digital VLSI implementation of ultra-discrete Burgers cellular automata for simulating traffic flow," Proceedings of the IEEE International Symposium on Communications and Information Technologies 2004, pp. 394-397, Sapporo, Japan (Oct. 26-29, 2004).
  125. Oya T., Asai T., Kagaya R., Hirose T., and Amemiya Y., "A competitive neural network with neuromorphic single-electron circuits," Proceedings of the 5th International Conference on Biological Physics, B09-342, Gothenburg, Sweden (Aug. 23-27, 2004).
  126. Ikebe M., Asai T., Hirose T., and Amemiya Y., "A quadrilateral-object composer for binary images with reaction-diffusion cellular automata," Proceedings of the 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pp. 406-409, Fukuoka, Japan (Aug. 4-6, 2004).
  127. Asai T., Kanazawa Y., Hirose T., and Amemiya Y., "A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection," Proceedings of the 2004 International Joint Conference on Neural Networks , W107, Budapest, Hungary (Jul. 25-29, 2004).
  128. Oya T., Asai T., and Amemiya Y., "Discrete dynamical behavior of a coupled SET oscillator," Satellite Session on Quantum Nano Electronics for Meme-Media-Based Information Technologies; the 7th Hokkaido University - Seoul National University Joint Symposium, Sapporo, Japan (Jul. 8-9, 2004).
  129. Oya T., Asai T., and Amemiya Y., "A single-electron device for an analog computation," Proceedings of the 2004 Silicon Nanoelectronics Workshop, pp. 123-124, Honolulu, U.S.A. (Jun. 13-14, 2004).
  130. Nakada K., Asai T., and Amemiya Y., "An analog CMOS circuit implementing a CNN-based locomotion controller for quadruped walking robots," Proceedings of the 2004 IEEE International Symposium on Circuits and Systems , vol. 3, pp. 1-4, Vancouver, Canada (May 23-26, 2004).
  131. Asai T., Kanazawa Y., Ikebe M., and Amemiya Y., "A MOS circuit for the Lotka-Volterra chaotic oscillator," Proceedings of the 12th International IEEE Workshop on Nonlinear Dynamics of Electronic Systems, pp. 71-74, Evora, Portugal (May 9-13, 2004).
  132. Kagaya R., Ikebe M., Asai T., and Amemiya Y., "On-chip fixed-pattern-noise canceling with non-destructive intermediate readout circuitry for CMOS active-pixel sensors," 4th WSEAS International Conference on Instrumentation, Measurement, Control, Circuits and Systems, Miami, U.S.A. (Apr. 21-23, 2004).
  133. Asai T., Kanazawa Y., Ikebe M., and Amemiya Y., "A Neuromorphic CMOS Family and its Application," International Symposium on Bio-Inspired Systems, P8-5, Kitakyushu, Japan (Mar. 7-9, 2004).
  134. Oya T., Asai T., and Amemiya Y., "Single-electron device for nonlinear analog computation ," 2004 RCIQE International Seminar for 21st Century COE Program: Quantum Nanoelectronics for Meme-Media-Based Information Technologies (II), Sapporo, Japan (Feb. 9-11, 2004).
  135. Nakada K., Asai T., and Amemiya Y., "An experimental chip for bio-inspired locomotion controller based on the Wilson-Cowan neural oscillator ," 2004 RCIQE International Seminar for 21st Century COE Program: Quantum Nanoelectronics for Meme-Media-Based Information Technologies (II), Sapporo, Japan (Feb. 9-11, 2004).
  136. Nakada K., Asai T., and Amemiya Y., "A novel analog cellular neural network for biologically-inspired walking robot," The 46th IEEE Midwest Symposium on Circuits and Systems , 576N, Cairo, Egypt (Dec. 27-30, 2003).
  137. Oya T., Kanazawa Y., Takahasi Y., Asai T., and Amemiya Y., "Single-electron device imitating reaction-diffusion systems," 6th International Conference on New Phenomena in Mesoscopic Systems and 4th International Conference on Surfaces and Interfaces in Mesoscopic Devices, P2.27, Hawaii, U.S.A. (Nov. 30-Dec. 5, 2003).
  138. Takahasi Y., Oya T., Asai T., and Amemiya Y., "Single-electron circuit as a discrete dynamical system," 6th International Conference on New Phenomena in Mesoscopic Systems and 4th International Conference on Surfaces and Interfaces in Mesoscopic Devices, P2.29, Hawaii, U.S.A. (Nov. 30-Dec. 5, 2003).
  139. Nakada K., Asai T., and Amemiya Y., "An analog CMOS circuit for locomotion control in quadruped walking robot," The 1st International Workshop on Ubiquitous Knowledge Network Environment, Sapporo, Japan (Nov. 25-27, 2003).
  140. Asai T. and Amemiya Y., "Nature-inspired analog computing on silicon," The 1st International Workshop on Ubiquitous Knowledge Network Environment, Sapporo, Japan (Nov. 25-27, 2003).
  141. Kanazawa Y., Asai T., and Amemiya Y., "A hardware depressing synapse and its application to contrast-invariant pattern recognition," The Society of Instrument and Control Engineers (SICE) Annual Conference 2003, TAI-11-2, Fukui, Japan (Aug. 4-6, 2003).
  142. Nakada K., Asai T., and Amemiya Y., "An analog neural oscillator circuit for locomotion control in quadruped walking robot," Proceedings of the 2003 International Joint Conference on Neural Networks , vol. 2, pp. 983-988, Oregon, U.S.A. (Jul. 20-24, 2003).
  143. Oya T., Ueno T., Asai T., and Amemiya Y., "Reaction-diffusion systems using single-electron oscillators," Abstract of the 2003 Silicon Nanoelectronics Workshop, pp. 82-83, Kyoto, Japan (Jun. 8-9, 2003).
  144. Takahasi Y., Oya T., Asai T., and Amemiya Y., "A single-electron oscillator with a multiple tunneling junction," Abstract of the 2003 Silicon Nanoelectronics Workshop, pp. 98-99, Kyoto, Japan (Jun. 8-9, 2003).
  145. Kanazawa Y., Asai T., and Amemiya Y., "An analog CMOS circuit emulating the Belousov-Zhabotinsky reaction," Proceedings of the 11th International IEEE Workshop on Nonlinear Dynamics of Electronic Systems, pp. 117-120, Scuol, Switzerland (May 18-21, 2003).
  146. Nakada K., Asai T., and Amemiya Y., "An analog CMOS circuit implementing CPG controller for quadruped walking robot," Proceedings of the 2nd International Symposium on Adaptive Motion of Animals and Machines , WeP-II-2, Kyoto, Japan (Mar. 4-8, 2003).
  147. Daikoku T., Asai T., and Amemiya Y., "An analog CMOS circuit implementing Turing's reaction-diffusion model," Proceedings of the 2002 International Symposium on Nonlinear Theory and its Applications, pp. 809-812, Xi'an, People's Republic of China (Oct. 7-11, 2002).
  148. Kanazawa Y., Yamada T., Asai T., and Amemiya Y., "Wireless synaptic / neuro devices based on interactions of local electric-fields and CDMA communication technology," 2002 IEEE International Conference on Systems, Man and Cybernetics, WA1P3, Hammamet, Tunisia (Oct. 6-9, 2002).
  149. Yamada T., Honma Y., Asai T., and Amemiya Y., "Reaction-diffusion chip implementing analog cellular-automaton model," Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials, pp. 368-369, Nagoya, Japan (Sep. 17-20, 2002).
  150. Oya T., Asai T., Fukui T., and Amemiya Y., "A majority-logic device using a single-electron box," Proceedings of the 2002 Silicon Nanoelectronics Workshop, pp. 79-80, Honolulu, U.S.A. (Jun. 9-10, 2002).
  151. Yamada T., Asai T., and Amemiya Y., "An excitable membrane device using minority carrier transport in semiconductors," Proceedings of the 6th International Conference on Cognitive and Neural Systems, II-#37, Boston, U.S.A. (May 29-Jun. 1, 2002).
  152. Asai T. and Amemiya Y., "Frequency- and temporal-domain neural competition in analog integrate-and-fire neurochips," Proceedings of the 2002 International Joint Conference on Neural Networks, pp. 1337-1341, Honolulu, U.S.A. (May 12-17, 2002).
  153. Asai T., Nishimiya Y., and Amemiya Y., "A novel reaction-diffusion system based on minority-carrier transport in solid-state CMOS devices," Proceedings of the International Semiconductor Device Research Symposium, pp. 141-144, Washington DC, U.S.A. (Dec. 5-7, 2001).
  154. Nishimiya Y., Sunayama T., Asai T., and Amemiya Y., "Reaction-diffusion chip based on cellular-automaton processing," Proceedings of the International Symposium on Nonlinear Theory and its Applications, vol. 2, pp. 593-596, Miyagi, Japan (Oct. 28-Nov. 1, 2001).
  155. Nishimiya Y., Asai T., and Amemiya Y., "Reaction-diffusion devices using minority-carrier transport in semiconductors," Extended Abstract of the 2001 International Conference on Solid State Devices and Materials, pp. 404-405, Tokyo, Japan (Sep. 25-28, 2001).
  156. Asai T., Kato H., and Amemiya Y., "Analog CMOS implementation of diffusive Lotka-Volterra neural networks," INNS-IEEE International Joint Conference on Neural Networks, P-90, Washington DC, U.S.A. (Jul. 15-19, 2001).
  157. Kato H., Asai T., and Amemiya Y., "Reaction-diffusion neuro chips: analog CMOS implementation of locally coupled Wilson-Cowan oscillators," Proceedings of the 5th International Conference on Cognitive and Neural Systems, II-#41, Boston, U.S.A. (May 30-Jun. 2, 2001).
  158. Kasai S., Amemiya Y., and Hasegawa H., "GaAs Schottky wrap-gate binary-decision-diagram devices for realization of novel single-electron logic architecture," Technical Digest of the International Electron Device Meeting, pp. 585-588, San Francisco, U.S.A. (Dec. 11-13, 2000).
  159. Koutani M., Asai T., and Amemiya Y., "Analog-digital CMOS circuits for motion detection with direction-selective neural networks," Proceedings of the 7th International Conference on Neural Information Processing, vol. 1, pp. 624-629, Taejon, Korea (Nov. 14-18, 2000).
  160. Akazawa M., Fujiwara T., and Amemiya Y., "A three-dimensional cellular neural network circuit system using a νMOS circuit," Proceedings of the 2000 IEEE International Symposium on Intelligent Signal Processing and Communication Systems, vol. 2 (D8-3-4), pp. 1061-1066, Honolulu, U.S.A. (Nov. 5-8, 2000).
  161. Inokuchi T., Yamada T., and Amemiya Y., "Analog Computation Using Quantum-Flux Parametron Devices," Abstracts of the 13th International Symposium on Superconductivity, p. 233, Tokyo, Japan (Oct. 14-16, 2000).
  162. Kinoshita Y., Yamada T., Kasai S., Amemiya Y., and Hasegawa H., "Quantum-dot logic systems based on the shared binary-decision diagram," Collected Abstracts of the 2000 International Symposium on Formation Physics and Device Applications of Quantum Dot Structures, p. 124, Sapporo, Japan (Sep. 10-14, 2000).
  163. Sunayama T., Asai T., Amemiya Y., and Ikebe M., "A νMOS vision chip based on the cellular-automaton processing," Extended Abstracts of the 2000 International Conference on Solid State Devices and Materials, pp. 364-365, Sendai, Japan (Aug. 30-31, 2000).
  164. Asai T., Koutani M., and Amemiya Y., "An analog-digital hybrid CMOS circuit for two-dimensional motion detection with correlation neural networks," Proccedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, vol. 3, pp. 494-499, Como, Italy (Jul. 24-27, 2000).
  165. Asai T. and Amemiya Y., "An analog-digital hybrid LSI for Hough transformation," Proceedings of the 4th International Conference on Cognitive and Neural Systems, I-#32, Boston, U.S.A. (May 24-27, 2000).
  166. Asai T., Amemiya Y., and Koshiba M., "A photonic-crystal logic circuit based on the binary decision diagram," International Workshop on Photonic and Electromagnetic Crystal Structures, T4-14, Sendai, Japan (Mar. 8-10, 2000).
  167. Yamada T. and Amemiya Y., "Multiple-valued logic devices using single-electron circuits," The International Workshop on Surfaces and Interfaces of Mesoscopic Devices, session 9 (no. 5), Kaanapali, U.S.A. (Dec. 6-10, 1999).
  168. Sunayama T., Ikebe M., and Amemiya Y., "A νMOS cellular-automaton device for differential-of-Gaussian Filtering," Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, pp. 110-111, Tokyo, Japan (Sep. 20-24, 1999).
  169. Wong Z.-S., Ikebe M., and Amemiya Y., "A νMOS cellular-automaton device for picture processing," Proceedings of the 8th International Symposium on Integrated circuits, Devices and Systems, pp. 331-334, Grand Hyatt, Singapore (Sep. 8-11, 1999).
  170. Yamada T., Ikebe M., and Amemiya Y., "A current-mode νMOS circuit for cellular automaton devices," Proceedings of the International Symposium on Future of Intellectual Integrated Electronics, pp. 383-388, Sendai, Japan (Mar. 14-17, 1999).
  171. Ikebe M. and Amemiya Y., "A νMOS cellular-automaton circuit for picture processing," Proceedings of the International Symposium on Future of Intellectual Integrated Electronics, pp. 377-382, Sendai, Japan (Mar. 14-17, 1999).
  172. Asahi N., Yamada T., Akazawa M., and Amemiya Y., "Single-flux-quantum logic devices based on the binary decision diagram," Proceedings of the 11th International Symposium on Superconductivity, pp. 1721-1724, Fukuoka, Japan (Nov. 16-19, 1998).
  173. Ikebe M., Akazawa M., and Amemiya Y., "Neu-MOS cellular automaton devices for intelligent image sensors," Proceedings of the 5th International Conference on Soft Computing and Information / Intelligent Systems, vol. 1, pp. 447-453, Iizuka, Japan (Oct. 16-20, 1998).
  174. Asahi N., Akazawa M., and Amemiya Y., "Construction of single-electron logic systems based on the binary decision diagram," International Symposium of Formation, Physics and Device Application of Quantum Dot Structures, Sapporo, Japan (May 31-Jun. 4, 1998).
  175. Tabe M., Terao Y., Asahi N., and Amemiya Y., "Simulation of visible light induced effects in a tunnel junction array for photonic device applications," International Symposium of Formation, Physics and Device Application of Quantum Dot Structures, Sapporo, Japan (May 31-Jun. 4, 1998).
  176. Ikebe M., Akazawa M., and Amemiya Y., "Neu-MOS cellular automaton circuits for intelligent image sensors," Proceedings of the Second International Conference on Knowledge-Based Intelligent Electronic Systems, pp. 447-453, Adelaide, Australia (Apr. 21-23, 1998).
  177. Asahi N., Akazawa M., and Amemiya Y., "Single-electron logic circuits based on the binary decision diagram," The 3rd International Workshop on Quantum Functional Devices, NIST, Gaithersberg, Maryland (Nov. 5-7, 1997).
  178. Wu N.-J., Shibata N., and Amemiya Y., "Quantum-Boltzmann-machine neuron device," Extended Abstracts of the 1997 International Conference on Solid State Devices and Materials, pp. 496-497, Hamamatsu, Japan (Sep. 16-19, 1997).
  179. Akazawa M., Yamada T., and Amemiya Y., "Computer-aided design of single-electron Boltzmann machine neuron circuit," Proceedings of the international conference on Simulation of Semiconductor Processes and Devices, pp. 201-204, Cambridge, U.S.A. (Sep. 8-10, 1997).
  180. Tabe M., Asahi N., Amemiya Y., and Terao Y., "Simulations of relaxation process of non-equilibrium electron distribution in two-dimensional tunnel junction array," International Symposium of Formation, Physics and Device Application of Quantum Dot Structures, Sapporo, Japan (Jan. 1-2, 1996).
  181. Wu N.-J., Asahi N., and Amemiya Y., "Single-electron-tunneling cellular automaton circuits," International Symposium of Formation, Physics and Device Application of Quantum Dot Structures, Sapporo, Japan (Jan. 1-2, 1996).

受賞

  1. 雨宮 佳希, "再構成可能な分子シナプス素子の簡易モデル," 第34回回路とシステムワークショップ - 奨励賞, 2022年3月11日.
  2. Ueno K., Asai T., and Amemiya Y., "A 0.02-to-2-MHz tunable clock reference circuit for intermittent pulse generators," 2009 IEEJ International Analog VLSI Workshop - Best Paper Award, Nov. 2009.
  3. Utagawa A., Asai T., Hirose T., and Amemiya Y., "An inhibitory neural network circuit exhibiting noise shaping with subthreshold MOS neuron circuits," The Research Institute of Signal Processing - NSCP'07 Outstanding Student Paper Award, Mar. 2007.
  4. Yamada K., Asai T., Motoike I.N., and Amemiya Y., "On digital VLSI circuits exploiting collision-based fusion gates," International Workshop From Utopian to Genuine Unconventional Computers - Best Paper Award, Sep. 2006.
  5. Oya T., Asai T., and Amemiya Y., "A single-electron reaction-diffusion device for computation of a Voronoi diagram," Workshop on Unconventional Computing - Best Paper Award, Sep. 2005.
  6. Ikebe M., Akazawa M., and Amemiya Y., "Neu-MOS cellular automaton devices for intelligent image sensors," 5th International Conference on Soft Computing and Information / Intelligent Systems - Best Paper Award, Oct. 1998.

国内学会

  1. 萩原 成基, 雨宮 佳希, アリ ホセ エミリアーノ, 浅井 哲也, 赤井 恵, "立体配線型メモリ素子で構成される新規脳型回路アーキテクチャの検討," 電子情報通信学会複雑コミュニケーションサイエンス研究会, 北海道 ルスツリゾートホテル&コンベンション, (ハイブリッド開催), 2022年3月27日.
  2. 雨宮 佳希, アリ ホセ エミリアーノ, 赤井 恵, 浅井 哲也, "再構成可能な分子シナプス素子の簡易モデル," 第34回 回路とシステムワークショップ, 北九州国際会議場, (小倉), 2021年8月26-27日.
  3. アリ ホセ エミリアーノ, 雨宮 佳希, 浅井 哲也, 赤井 恵, "Neuromorphic Devices using Spatial Free Wiring of Conductive Polymer for Hardware Artificial Neural Networks," 電子情報通信学会複雑コミュニケーションサイエンス研究会, (オンライン開催), 2021年3月29日.

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