北海道大学 大学院情報科学研究院

学術論文

1. Yamamoto K., Kawamura K., Ando K., Mertig N., Takemoto T., Yamaoka M., Teramoto H., Sakai A., Takamaeda-Yamazaki S., and Motomura M., "STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin–Spin Interactions," IEEE Journal of Solid-State Circuits, vol. 56, no. 1, pp. 165-178 (2020).
2. Yamamoto K., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "FPGA-based annealing processor with time-division multiplexing," IEICE Transactions on Information and Systems, vol. E102-D, no. 12, pp. 2295-2305 (2019).
3. Yamamoto K., Ikebe M., Asai T., and Motomura M., "FPGA-based stream processing for frequent itemset mining with incremental multiple hashes," Circuits and Systems, vol. 7, no. 10, pp. 3299-3309 (2016).

国際会議

1. Yamamoto K., Ando K., Mertig N., Takemoto T., Yamaoka M., Teramoto H., Sakai A., Takamaeda-Yamazaki S., and Motomura M., "STATICA: A 512-spin 0.25M-weight full-digital annealing processor with a near-memory all-spin-updates-at-once architecture for combinatorial optimization with complete spin-spin interactions," 2020 International Solid-State Circuits Conference (ISSCC 2020), San Francisco Marriott Marquis, San Francisco, USA (Feb. 16-20, 2020).
2. Yamamoto K., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S., "Time-Division Multiplexing ," GI-CoRE GSQ, GSB, & IGM Joint Symposium -Quantum, Informatics, Biology, & Medicine -, Hokkaido University, Sapporo, Japan (Jul. 10-11, 2017).
3. Yamamoto K., Huang W., Takamaeda-Yamazaki S., Ikebe M., Asai T., and Motomura M., "A Time-Division Multiplexing Ising Machine on FPGAs," International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2017), Ruhr University, Bochum, Germany (Jun. 7-9, 2017).
4. Yamamoto K., Takamaeda-Yamazaki S., Ikebe M., Asai T., and Motomura M., "A scalable ising model implementation on an FPGA," COOL Chips 20, Yokohama Media & Communications Center, Yokohama, Japan (Apr. 19-21, 2017).
5. Yamamoto K., Asai T., and Motomura M., "Hardware architecture for online frequent items mining with memory-efficient data structure," COOL Chips XIX, Yokohama Media & Communications Center, Yokohama, Japan (Apr. 20-22, 2016).
6. Yamamoto K., Fukuda E.S., Asai T., and Motomura M., "An accelerator for frequent Itemset mining from data stream with parallel item tree," The 19th Workshop on Synthesis And System Integration of Mixed Information Technologies, Evergreen Resort Hotel, Yilan, Taiwan (Mar. 16-17, 2015).

受賞

1. 山本 和輝, "サブスレッショルドCMOS LSIのためのナノワットDA変換器," 電子情報通信学会集積回路研究会 - 12月度学生・若手研究会 優秀若手研究ポスター賞, Mar. 2010.

国内学会

1. 山本 和輝, 上野 憲一, 浅井 哲也, 雨宮 好仁, "時間軸上のパルス加算による低電力DA変換器," 電子情報通信学会総合大会, (仙台), 2010年3月.
2. 山本 和輝, 上野 憲一, 浅井 哲也, 雨宮 好仁, "サブスレッショルドCMOS LSIのためのナノワットDA変換器," 電子情報通信学会 集積回路研究会, (静岡), 2009年12月.
3. 山本 和輝, 飯田 智貴, 浅井 哲也, 雨宮 好仁, "サブスレッショルドMOS回路のためのナノアンペア電流源," 電子情報通信学会ソサイエティ大会, (新潟), 2009年9月.